From 6185f80c311cc3bdef2f8d5096c61e40ca6f48b2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:53 +0400 Subject: net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYs This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 1568310..df6f7c9 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -670,6 +670,7 @@ typedef enum enet_interface { ENET_1000_RGMII, ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, + ENET_1000_RGMII_TXID, ENET_1000_TBI, ENET_1000_RTBI, ENET_1000_SGMII diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index aa4eb5e..9715183 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -429,12 +429,23 @@ static int marvell_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; + enum enet_interface iface = uec->uec_info->enet_interface; - if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) { + if (iface == ENET_1000_RGMII_ID || + iface == ENET_1000_RGMII_RXID || + iface == ENET_1000_RGMII_TXID) { int temp; temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); - temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); + if (iface == ENET_1000_RGMII_ID) { + temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; + } else if (iface == ENET_1000_RGMII_RXID) { + temp &= ~MII_M1111_TX_DELAY; + temp |= MII_M1111_RX_DELAY; + } else if (iface == ENET_1000_RGMII_TXID) { + temp &= ~MII_M1111_RX_DELAY; + temp |= MII_M1111_TX_DELAY; + } phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); -- cgit v1.1 From d77c779bc23596aa3693d1c5c4d5b6e1072f93f2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:55 +0400 Subject: net: uec: Fix uccf.h and uec.h headers to include headers they depend on Headers should include headers containing prototypes and defines they depend on, don't assume that they're included by somebody else. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- drivers/qe/uccf.h | 1 + drivers/qe/uec.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 1ff9e1d..2404c6a 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -25,6 +25,7 @@ #include "common.h" #include "qe.h" +#include "asm/immap_qe.h" /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index df6f7c9..febfbce 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -23,6 +23,9 @@ #ifndef __UEC_H__ #define __UEC_H__ +#include "qe.h" +#include "uccf.h" + #define MAX_TX_THREADS 8 #define MAX_RX_THREADS 8 #define MAX_TX_QUEUES 8 -- cgit v1.1 From 034477bb31948d698d18b84bc0834c3e25a14d04 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:57 +0400 Subject: mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is available Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index dc4dbd3..769eb2f 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -126,6 +126,7 @@ phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; + u32 lbc_sdram_size; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -147,7 +148,9 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - msize += sdram_init(msize * 1024 * 1024); + lbc_sdram_size = sdram_init(msize * 1024 * 1024); + if (!msize) + msize = lbc_sdram_size; /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); -- cgit v1.1 From 89da44ce3fe1638312d71cb3add8c6a6d2c7c1f3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:59 +0400 Subject: mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 56 +++++++++++++++++++++++++++---- include/configs/MPC8360EMDS.h | 4 +-- 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 769eb2f..54f2989 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -21,12 +21,14 @@ #endif #include #include +#include #if defined(CONFIG_OF_LIBFDT) #include #endif #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif +#include "../../../drivers/qe/uec.h" const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -89,11 +91,19 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; -int board_early_init_f(void) +/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ +static int board_handle_erratum2(void) { + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; + return REVID_MAJOR(immr->sysconf.spridr) == 2 && + REVID_MINOR(immr->sysconf.spridr) == 1; +} + +int board_early_init_f(void) +{ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[0xa] &= ~0x04; @@ -105,6 +115,21 @@ int board_early_init_f(void) /* Enable second UART */ bcsr[0x9] &= ~0x01; + if (board_handle_erratum2()) { + void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); + + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits_be32(immap, 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32(immap + 4, 0xff0, 0xaa0); + } return 0; } @@ -116,6 +141,28 @@ int board_early_init_r(void) return 0; } +#ifdef CONFIG_UEC_ETH +static uec_info_t uec_info[] = { +#ifdef CONFIG_UEC_ETH1 + STD_UEC_INFO(1), +#endif +#ifdef CONFIG_UEC_ETH2 + STD_UEC_INFO(2), +#endif +}; + +int board_eth_init(bd_t *bd) +{ + if (board_handle_erratum2()) { + int i; + + for (i = 0; i < ARRAY_SIZE(uec_info); i++) + uec_info[i].enet_interface = ENET_1000_RGMII_RXID; + } + return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); +} +#endif /* CONFIG_UEC_ETH */ + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -312,8 +359,6 @@ static int sdram_init(unsigned int base) { return 0; } #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); @@ -323,8 +368,7 @@ void ft_board_setup(void *blob, bd_t *bd) * if on mpc8360ea rev. 2.1, * change both ucc phy-connection-types from rgmii-id to rgmii-rxid */ - if ((REVID_MAJOR(immr->sysconf.spridr) == 2) && - (REVID_MINOR(immr->sysconf.spridr) == 1)) { + if (board_handle_erratum2()) { int nodeoffset; const char *prop; int path; diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b072e84..fec7cc5 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -397,7 +397,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -408,7 +408,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif /* -- cgit v1.1 From da6eea0f48c24a318e6de69d6bca0bb5ab70572b Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:22:08 +0400 Subject: mpc83xx: mpc8360emds: Add QE USB device tree fixups With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8360emds/mpc8360emds.c | 12 ++++++++++++ include/configs/MPC8360EMDS.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 54f2989..d4ba043 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -25,6 +25,8 @@ #if defined(CONFIG_OF_LIBFDT) #include #endif +#include +#include #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif @@ -357,12 +359,22 @@ static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) +static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) +{ + if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) + return; + + do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", + "peripheral", sizeof("peripheral"), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + ft_board_fixup_qe_usb(blob, bd); /* * mpc8360ea pb mds errata 2: RGMII timing * if on mpc8360ea rev. 2.1, diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fec7cc5..62cf13b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -382,6 +382,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HWCONFIG 1 + /* * QE UEC ethernet configuration */ -- cgit v1.1 From 00ec0ff549b8cb6fb6d40e275aeb5a460642a3bd Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:44:51 -0400 Subject: sbc8349: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker Signed-off-by: Kim Phillips --- Makefile | 15 +-------------- include/configs/sbc8349.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/Makefile b/Makefile index 9c5b2a5..8ab864d 100644 --- a/Makefile +++ b/Makefile @@ -2403,20 +2403,7 @@ MVBLM7_config: unconfig sbc8349_config \ sbc8349_PCI_33_config \ sbc8349_PCI_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _PCI_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST at " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "33MHz... " ; \ - echo "#define PCI_33M" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "66MHz... " ; \ - echo "#define PCI_66M" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349 + @$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349 SIMPC8313_LP_config \ SIMPC8313_SP_config: unconfig diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3..6f574ca 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -32,6 +32,21 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#endif + +#ifdef CONFIG_MK_66 +#define PCI_66M +#endif + +#ifdef CONFIG_MK_33 +#define PCI_33M +#endif + +/* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -- cgit v1.1 From c7190f028fa950d4d36b6d0b4bb3fc72602ec54c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS__ assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 261 +++++++++++++++++++++++++----------------- include/configs/MPC8313ERDB.h | 3 +- include/configs/MPC8315ERDB.h | 3 +- include/configs/MPC8323ERDB.h | 3 +- include/configs/MPC832XEMDS.h | 3 +- include/configs/MPC8349EMDS.h | 3 +- include/configs/MPC8349ITX.h | 3 +- include/configs/MPC8360EMDS.h | 3 +- include/configs/MPC8360ERDK.h | 3 +- include/configs/MPC837XEMDS.h | 3 +- include/configs/MPC837XERDB.h | 3 +- include/configs/MVBLM7.h | 3 +- include/configs/SIMPC8313.h | 4 +- include/configs/TQM834x.h | 3 +- include/configs/kmeter1.h | 4 +- include/configs/sbc8349.h | 3 +- include/configs/vme8349.h | 3 +- 17 files changed, 188 insertions(+), 123 deletions(-) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 5c930d3..031e8d5 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include #include #include -#ifdef CONFIG_USB_EHCI_FSL #include +#ifdef CONFIG_USB_EHCI_FSL #include #endif @@ -63,149 +63,163 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* system performance tweaking */ - -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + __be32 acr_mask = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | #endif - + 0; + __be32 acr_val = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif + 0; + __be32 spcr_mask = +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ + (SPCR_OPT << SPCR_OPT_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | +#endif + 0; + __be32 spcr_val = #ifdef CONFIG_SYS_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSECEP - /* all eTSEC's Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC1EP - /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC2EP - /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_ENCCM - /* Encryption clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); + 0; + __be32 sccr_mask = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_PCICM - /* PCI & DMA clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT); +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (SCCR_PCICM << SCCR_PCICM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSECCM - /* all TSEC's clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1CM - /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2CM - /* TSEC2 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1ON - /* TSEC1 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2ON - /* TSEC2 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBMPHCM - /* USB MPH clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBDRCM - /* USB DR clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_SATACM - /* SATA controller clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT); +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + __be32 sccr_val = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | #endif +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); + + clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); + + clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); /* RSR - Reset Status Register - clear all status (4.6.1.3) */ - gd->reset_status = im->reset.rsr; - im->reset.rsr = ~(RSR_RES); + gd->reset_status = __raw_readl(&im->reset.rsr); + __raw_writel(~(RSR_RES), &im->reset.rsr); /* AER - Arbiter Event Register - store status */ - gd->arbiter_event_attributes = im->arbiter.aeatr; - gd->arbiter_event_address = im->arbiter.aeadr; + gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); + gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr); /* * RMR - Reset Mode Register * contains checkstop reset enable (4.6.1.4) */ - im->reset.rmr = (RMR_CSRE & (1<lbus.lcrr = CONFIG_SYS_LCRR; + __raw_writel(RMR_CSRE & (1<reset.rmr); - /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ - im->sysconf.spcr |= SPCR_TBEN; + /* Enable Time Base & Decrementer ( so we will have udelay() )*/ + setbits_be32(&im->sysconf.spcr, SPCR_TBEN); /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH; + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + &im->sysconf.sicrh); #else - im->sysconf.sicrh = CONFIG_SYS_SICRH; + __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif #ifdef CONFIG_SYS_SICRL - im->sysconf.sicrl = CONFIG_SYS_SICRL; + __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); #endif - /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif - /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif #ifdef CONFIG_QE @@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im) /* Wait for clock to stabilize */ do { - temp = in_be32(&ehci->control); + temp = __raw_readl(&ehci->control); udelay(1000); } while (!(temp & PHY_CLK_VALID)); #endif @@ -317,8 +331,41 @@ void cpu_init_f (volatile immap_t * im) int cpu_init_r (void) { + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif + __be32 lcrr_mask = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ + LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + LCRR_CLKDIV | +#endif + 0; + __be32 lcrr_val = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + CONFIG_SYS_LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC + CONFIG_SYS_LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + CONFIG_SYS_LCRR_CLKDIV | +#endif + 0; + + /* LCRR - Clock Ratio Register (10.3.1.16) + * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description + */ + clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->lbus.lcrr); + isync(); + +#ifdef CONFIG_QE qe_init(qe_base); qe_reset(); #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 76b7894..5927e76 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -216,7 +216,8 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 84cc9fa..8eaff5d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -182,7 +182,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c40d3d3..356586c 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -170,7 +170,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f16616c..f17f9c7 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -159,7 +159,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9b2d25a..6361c45 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -206,7 +206,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 3b4e344..eaa59fd 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 62cf13b..8520155 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -185,7 +185,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index cb0535c..6cee78a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -177,7 +177,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a190a50..abeb6a2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -220,7 +220,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 89fafe7..7ef92f7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -243,7 +243,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9835567..f8b016f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -137,7 +137,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 866ff17..f68d834 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -111,7 +111,9 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index da08b7c..4c909e6 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -52,7 +52,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 /* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 79d8638..bec08da 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -170,7 +170,9 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 /* * Init Local Bus Memory Controller: diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6f574ca..bf7cf82 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -197,7 +197,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 5304ec9..d0690fe 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -178,7 +178,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ -- cgit v1.1