From 14dab831e8e93a7ee03de2c7cca00d4b81e00cdc Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Fri, 9 Dec 2011 16:03:02 +0800 Subject: ENGR00163697 - FEC : Adjust MX53 Network stream throughput. - When the system is very busy(such as play 1080p streaming in local) the WIFI & FEC performance were very low. - Enable the patch in uboot for WIFI and FEC performance: If WIFI connect to PORT2, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT2 If WIFI connect to port3, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT3 - The solution of the patch: I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the high rate of accessing bus. II. Increase Master 4 priority for FEC. Increase Master 2 and AHBMAX priority for WIFI. - Test result: i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec. Signed-off-by: Fugang Duan --- board/freescale/mx53_ard/lowlevel_init.S | 110 ++++++++++++++++++++++++++++++ board/freescale/mx53_evk/lowlevel_init.S | 110 ++++++++++++++++++++++++++++++ board/freescale/mx53_loco/lowlevel_init.S | 110 ++++++++++++++++++++++++++++++ board/freescale/mx53_pcba/lowlevel_init.S | 110 ++++++++++++++++++++++++++++++ board/freescale/mx53_smd/lowlevel_init.S | 110 ++++++++++++++++++++++++++++++ 5 files changed, 550 insertions(+) diff --git a/board/freescale/mx53_ard/lowlevel_init.S b/board/freescale/mx53_ard/lowlevel_init.S index 67cfe2e..1ce5f70 100644 --- a/board/freescale/mx53_ard/lowlevel_init.S +++ b/board/freescale/mx53_ard/lowlevel_init.S @@ -90,6 +90,111 @@ beq 1b .endm +.macro init_m4if + /*increase master2 priority for WIFI*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x40] + orr r1, r1, #(0x33 << 16) + str r1, [r0, #0x40] + + /*increase master4 priority for FEC*/ + ldr r1, [r0, #0x44] + orr r1, r1, #0x33 + str r1, [r0, #0x44] + + /*set SDHC-port3 high priority to all AHB MAX Slave port*/ + ldr r0, =AHBMAX_BASE_ADDR + +#ifdef CONFIG_WIFI_SDHC_PORT3 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port3 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xb00] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x1 +#endif + +#ifdef CONFIG_WIFI_SDHC_PORT2 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port2 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xA00] + bic r1, r1, #(0x7 << 0) +#endif + + /*set JMP step to zero*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x48] + bic r1, r1, #(0x3 << 8) + str r1, [r0, #0x48] +.endm + .macro init_clock ldr r0, =ROM_SI_REV ldr r1, [r0] @@ -232,6 +337,11 @@ lowlevel_init: init_aips +#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE + /*increase WIFI & FEC priority of accessing bus*/ + init_m4if +#endif + init_clock mov pc, lr diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S index 5e068ff..03c550f 100644 --- a/board/freescale/mx53_evk/lowlevel_init.S +++ b/board/freescale/mx53_evk/lowlevel_init.S @@ -90,6 +90,111 @@ beq 1b .endm +.macro init_m4if + /*increase master2 priority for WIFI*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x40] + orr r1, r1, #(0x33 << 16) + str r1, [r0, #0x40] + + /*increase master4 priority for FEC*/ + ldr r1, [r0, #0x44] + orr r1, r1, #0x33 + str r1, [r0, #0x44] + + /*set SDHC-port3 high priority to all AHB MAX Slave port*/ + ldr r0, =AHBMAX_BASE_ADDR + +#ifdef CONFIG_WIFI_SDHC_PORT3 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port3 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xb00] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x1 +#endif + +#ifdef CONFIG_WIFI_SDHC_PORT2 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port2 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xA00] + bic r1, r1, #(0x7 << 0) +#endif + + /*set JMP step to zero*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x48] + bic r1, r1, #(0x3 << 8) + str r1, [r0, #0x48] +.endm + .macro init_clock ldr r0, =ROM_SI_REV ldr r1, [r0] @@ -232,6 +337,11 @@ lowlevel_init: init_aips +#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE + /*increase WIFI & FEC priority of accessing bus*/ + init_m4if +#endif + init_clock mov pc, lr diff --git a/board/freescale/mx53_loco/lowlevel_init.S b/board/freescale/mx53_loco/lowlevel_init.S index 8308e95..ba8ce6d 100644 --- a/board/freescale/mx53_loco/lowlevel_init.S +++ b/board/freescale/mx53_loco/lowlevel_init.S @@ -88,6 +88,111 @@ beq 1b .endm +.macro init_m4if + /*increase master2 priority for WIFI*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x40] + orr r1, r1, #(0x33 << 16) + str r1, [r0, #0x40] + + /*increase master4 priority for FEC*/ + ldr r1, [r0, #0x44] + orr r1, r1, #0x33 + str r1, [r0, #0x44] + + /*set SDHC-port3 high priority to all AHB MAX Slave port*/ + ldr r0, =AHBMAX_BASE_ADDR + +#ifdef CONFIG_WIFI_SDHC_PORT3 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port3 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xb00] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x1 +#endif + +#ifdef CONFIG_WIFI_SDHC_PORT2 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port2 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xA00] + bic r1, r1, #(0x7 << 0) +#endif + + /*set JMP step to zero*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x48] + bic r1, r1, #(0x3 << 8) + str r1, [r0, #0x48] +.endm + .macro init_clock ldr r0, =ROM_SI_REV ldr r1, [r0] @@ -230,6 +335,11 @@ lowlevel_init: init_aips +#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE + /*increase WIFI & FEC priority of accessing bus*/ + init_m4if +#endif + init_clock mov pc, lr diff --git a/board/freescale/mx53_pcba/lowlevel_init.S b/board/freescale/mx53_pcba/lowlevel_init.S index 7fb4c5c..30ff6b3 100644 --- a/board/freescale/mx53_pcba/lowlevel_init.S +++ b/board/freescale/mx53_pcba/lowlevel_init.S @@ -88,6 +88,111 @@ beq 1b .endm +.macro init_m4if + /*increase master2 priority for WIFI*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x40] + orr r1, r1, #(0x33 << 16) + str r1, [r0, #0x40] + + /*increase master4 priority for FEC*/ + ldr r1, [r0, #0x44] + orr r1, r1, #0x33 + str r1, [r0, #0x44] + + /*set SDHC-port3 high priority to all AHB MAX Slave port*/ + ldr r0, =AHBMAX_BASE_ADDR + +#ifdef CONFIG_WIFI_SDHC_PORT3 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port3 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xb00] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x1 +#endif + +#ifdef CONFIG_WIFI_SDHC_PORT2 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port2 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xA00] + bic r1, r1, #(0x7 << 0) +#endif + + /*set JMP step to zero*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x48] + bic r1, r1, #(0x3 << 8) + str r1, [r0, #0x48] +.endm + .macro init_clock ldr r0, =ROM_SI_REV ldr r1, [r0] @@ -230,6 +335,11 @@ lowlevel_init: init_aips +#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE + /*increase WIFI & FEC priority of accessing bus*/ + init_m4if +#endif + init_clock mov pc, lr diff --git a/board/freescale/mx53_smd/lowlevel_init.S b/board/freescale/mx53_smd/lowlevel_init.S index 7bf9e69..0affe07 100644 --- a/board/freescale/mx53_smd/lowlevel_init.S +++ b/board/freescale/mx53_smd/lowlevel_init.S @@ -89,6 +89,111 @@ beq 1b .endm +.macro init_m4if + /*increase master2 priority for WIFI*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x40] + orr r1, r1, #(0x33 << 16) + str r1, [r0, #0x40] + + /*increase master4 priority for FEC*/ + ldr r1, [r0, #0x44] + orr r1, r1, #0x33 + str r1, [r0, #0x44] + + /*set SDHC-port3 high priority to all AHB MAX Slave port*/ + ldr r0, =AHBMAX_BASE_ADDR + +#ifdef CONFIG_WIFI_SDHC_PORT3 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x3 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port3 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xb00] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x1 +#endif + +#ifdef CONFIG_WIFI_SDHC_PORT2 + /*set PARK to SDHC-port3*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0x10] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x110] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x210] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + ldr r1, [r0, #0x310] + bic r1, r1, #(0x7 << 0) + orr r1, r1, #0x2 + bic r1, r1, #(0x3 << 4) + bic r1, r1, #(0x3 << 8) + orr r1, r1, #(0x1 << 30) + bic r1, r1, #(0x1 << 31) + + /*set SDHC-port2 arbitration*/ + ldr r0, =AHBMAX_BASE_ADDR + ldr r1, [r0, #0xA00] + bic r1, r1, #(0x7 << 0) +#endif + + /*set JMP step to zero*/ + ldr r0, =M4IF_BASE_ADDR + ldr r1, [r0, #0x48] + bic r1, r1, #(0x3 << 8) + str r1, [r0, #0x48] +.endm + .macro init_clock ldr r0, =ROM_SI_REV ldr r1, [r0] @@ -242,6 +347,11 @@ lowlevel_init: init_aips +#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE + /*increase WIFI & FEC priority of accessing bus*/ + init_m4if +#endif + init_clock mov pc, lr -- cgit v1.1