From 0b217456375bace3fbe9a72c7e92a46dc1907277 Mon Sep 17 00:00:00 2001
From: Robby Cai <robby.cai@nxp.com>
Date: Wed, 30 Nov 2016 22:05:03 +0800
Subject: MLK-13723 imx7d: restore epdc QoS setting after exit the lpsr mode

without this patch, the QoS setting will be lost after exit LPSR mode.
The patch moves the QoS setting into DDR setting group (in plugin mode), thus
when exit LPSR mode, QoS setting will be restored as well as DDR setting.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
---
 arch/arm/include/asm/arch-mx7/imx-regs.h        |  5 +++
 board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | 53 +++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a3106e7..899d94c 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -215,6 +215,11 @@
 #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
 #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
 #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
+#define REGS_QOS_BASE     QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC     (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0     (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1     (QOSC_IPS_BASE_ADDR + 0x3C00)
+
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
index 0c1db98..25eda85 100644
--- a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
+++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
@@ -414,6 +414,8 @@ TUNE_END:
 	cmp	r7, #0x1
 	bne	15b
 
+	imx7_qos_setting
+
 	/* enable port */
 	ldr	r7, =0x1
 	str	r7, [r3, #0x490]
@@ -588,6 +590,57 @@ wait_stat:
 .endm
 
 .macro imx7_qos_setting
+	ldr r0, =REGS_QOS_BASE
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r1, =0
+	str r1, [r0, #0x60]
+
+	ldr r0, =REGS_QOS_EPDC
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP1
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_EPDC
+	ldr r1, =0x0f020f22
+	str r1, [r0, #0xd0]
+	str r1, [r0, #0xe0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x1
+	str r1, [r0, #0]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020222
+	str r1, [r0, #0x50]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x50]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020222
+	str r1, [r0, #0x60]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x60]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020422
+	str r1, [r0, #0x70]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x70]
+
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0xe080
+	str r1, [r0, #0x34]
 .endm
 
 .macro imx7_ddr_setting
-- 
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