From 93cedc71647b4b72ac9b48e11997eb2f91645001 Mon Sep 17 00:00:00 2001 From: James Yang Date: Tue, 12 Jan 2010 15:50:18 -0600 Subject: ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2103e2e..8dab8d1 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[2] = sysclk; freqCC_PLL[3] = sysclk; - sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; - sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f); freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; -- cgit v1.1 From 693416fe01d324472d270ac28389022eb82c7217 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 25 Jan 2010 11:01:51 -0600 Subject: Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies" This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922. The original code was correct. I clearly need glasses or a brown paper bag. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 8dab8d1..9193992 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = sysInfo->freqSystemBus / 2; - else sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; - else sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; #endif #endif -- cgit v1.1 From 1118cdbfeb8fc3acfe542d08703153ac188f9dbd Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 7 Jan 2010 16:00:13 +0800 Subject: fsl_esdhc: fix wrong clock mask Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS. Signed-off-by: Jin Qing Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- include/fsl_esdhc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..eac6a2b 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 -- cgit v1.1 From d91803826985bfdf151eed66543ce3b1a301682f Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 27 Nov 2009 15:31:51 +0800 Subject: ppc/85xx: Add PIB/ATM support for MPC8569mds Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- board/freescale/common/pq-mds-pib.c | 2 +- board/freescale/mpc8569mds/mpc8569mds.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 6c72aa1..5f7a67d 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8360EMDS) +#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1c76b84..1eddeef 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -39,6 +39,9 @@ #include #include "bcsr.h" +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif phys_size_t fixed_sdram(void); @@ -545,6 +548,10 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); +#if defined(CONFIG_PQ_MDS_PIB) + pib_init(); +#endif + #ifdef CONFIG_PCIE1 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); -- cgit v1.1 From c95d541e4b46cb3ba19bf35e34b1dc3ca32f7b4b Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 27 Nov 2009 15:31:52 +0800 Subject: ppc/85xx: Add ATM config for MPC8569MDS Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- MAKEALL | 1 + Makefile | 3 ++- include/configs/MPC8569MDS.h | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index afdc1b5..15e93cf 100755 --- a/MAKEALL +++ b/MAKEALL @@ -403,6 +403,7 @@ LIST_85xx=" \ MPC8560ADS \ MPC8568MDS \ MPC8569MDS \ + MPC8569MDS_ATM \ MPC8572DS \ MPC8572DS_36BIT \ P2020DS \ diff --git a/Makefile b/Makefile index 722b976..69b963f 100644 --- a/Makefile +++ b/Makefile @@ -2489,8 +2489,9 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8569MDS_ATM_config \ MPC8569MDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8569mds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index e16f0e1..ae2fc19 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -51,6 +51,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CLK_FREQ 66666666 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_MK_ATM +#define CONFIG_PQ_MDS_PIB +#define CONFIG_PQ_MDS_PIB_ATM +#endif + /* * These can be toggled for performance analysis, otherwise use default. */ -- cgit v1.1 From 0fd2fa6cce6eb91271ebf9733878d0f1fcbc9b32 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 17 Nov 2009 20:49:05 +0800 Subject: Fix the local bus divider mapping The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 9193992..268edbc 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ +#if defined(CONFIG_FSL_CORENET) + /* If this is corenet based SoC, bit-representation + * for four times the clock divider values. + */ + lcrr_div *= 4; +#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) /* * Yes, the entire PQ38 family use the same -- cgit v1.1 From 46df64f22c471b010161aa68bfdbfe94ea46e7bd Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Fri, 15 Jan 2010 14:58:40 +0800 Subject: qe: fixup the snum for MPC8569 Rev2.0 Since 1.0 and 2.0 use different snum table, we fixup the snum value according to SPRN_SVR. Signed-off-by: Liu Yu Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index af0e78e..1d11ab4 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob) #define ft_fixup_dpaa_clks(x) #endif +#ifdef CONFIG_QE +static void ft_fixup_qe_snum(void *blob) +{ + unsigned int svr; + + svr = mfspr(SPRN_SVR); + if (SVR_SOC_VER(svr) == SVR_8569_E) { + if(IS_SVR_REV(svr, 1, 0)) + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 46, 1); + else + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 76, 1); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", gd->lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); + ft_fixup_qe_snum(blob); #endif #ifdef CONFIG_SYS_NS16550 -- cgit v1.1 From 66e821ebe96123b3a81ec9ca25cec9c0560fe232 Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Thu, 7 Jan 2010 14:27:14 +0530 Subject: 85xx/p1_p2_rdb: enable hwconfig Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 15bfeef..405e6d5 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -203,6 +203,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -- cgit v1.1