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* The patch introduces the CRITICAL feature of POST tests. If the test marked ↵Yuri Tikhonov2008-03-18-3/+15
| | | | | | | as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* The patch adds new POST tests for the Lwmon5 board. These are:Yuri Tikhonov2008-03-18-0/+811
| | | | | | | | | | | * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* Enable CODEC POST with CFG_POST_CODEC rather than with CFG_POST_DSP.Yuri Tikhonov2008-03-18-1/+1
| | | | Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
* ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-2/+0
| | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* Fix warnings while compilation of post/drivers/memory.cAnatolij Gustschin2008-03-02-3/+3
| | | | | | Fix warnings while compilation with new gcc in eldk-4.2 Signed-off-by: Anatolij Gustschin <agust@denx.de>
* POST: Disable cache while SPR POSTAnatolij Gustschin2008-03-02-0/+14
| | | | | | | | Currently (since commit b2e2142c) u-boot crashes on sequoia board while SPR test if CONFIG_4xx_DCACHE is enabled. This patch disables the cache while SPR test. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Fix CPU POST test failureYuri Tikhonov2008-02-21-0/+3
| | | | | | | | | | | | The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered by it. The gcc-4.2 with its more aggressive optimization exposes this fact. This patch just saves the CR value before running the test code, so allowing it to do anything it wants with CR. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> --
* Add attribute POST_PREREL to ECC memory POSTLarry Johnson2008-02-07-2/+2
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Refactor ECC POST for AMCC Denali coreLarry Johnson2008-01-16-131/+135
| | | | | | | | | | | | | The ECC POST reported intermittent failures running after power-up on the Korat PPC440EPx board. Even when the test passed, the debugging output occasionally reported additional unexpected ECC errors. This refactoring has three main objectives: (1) minimize the code executed with ECC enabled during the tests, (2) add more checking of the results so any unexpected ECC errors would cause the test to fail, and (3) use synchronization (only) where required by the processor. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc_4xx: Fix post spr.c for PPC405Niklaus Giger2008-01-14-0/+6
| | | | | | | post/cpu/ppc4xx/spr.c contained a few checks for registers only present for PPC440 and derivates processor. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* POST: Execute SPR test after relocationStefan Roese2008-01-09-1/+1
| | | | | | | | | | On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses self modifying code and this doesn't work with stack in d-cache, since I can't move the code from d-cache to i-cache. We move the SPR test to be executed a little later, after relocation. Then stack is located in SDRAM and this self-modifying code is no problem anymore. Signed-off-by: Stefan Roese <sr@denx.de>
* Cosmetic changes to ECC POST for AMCC Denali coreLarry Johnson2007-12-27-6/+6
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Fix compilation problem in 405 cache POST testStefan Roese2007-12-27-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem in 44x cache POST routineStefan Roese2007-12-27-22/+19
| | | | | | | | | | | As repoted by Larry Johnson, running "diag run cache" caused a crash in U-Boot. This problem was introduced by a patch that removed the TLB entry for the cache test after the test has completed. Since this TLB was only setup once, a 2nd attempt to run this cache test failed with a crash. Now this TLB entry is created every time the routine is called. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix lwmon5 compilation problemStefan Roese2007-12-27-29/+0
| | | | | | | Now that the 440EPx ECC test is not board specific anymore remove this Makefile. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix/enhance ECC POST for 440EPx/GRxLarry Johnson2007-12-27-46/+46
| | | | | | | | | This patch allows the ECC POST to be used for different boards with the PPC440 Denali SDRAM controller. Modifications include skipping the test if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization to prevent timing errors. Signed-off-by: Larry Johnson <lrj@acm.org>
* PPC4xx: Move/rename ECC POST for 440EPx/GRxLarry Johnson2007-12-27-0/+0
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: use correct io accessors for 4xx ethernet POSTMatthias Fuchs2007-12-27-21/+21
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Enable CPU POST test for 4xx with dcache enabledStefan Roese2007-10-31-0/+11
| | | | | | | | Now with caches enabled (i- and d-cache) on 44x, we need a chance to disable the cache for the CPU POST tests, since these tests consist of self modifying code. This is done via the new change_tlb() function. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change 4xx POST ethernet test to handle cached memory tooStefan Roese2007-10-31-1/+10
| | | | | | | This patch enables the 4xx EMAC POST driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove temporary TLB entry in POST cache test only for 440Stefan Roese2007-10-31-0/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove compiler warning from previous commitStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove temporary TLB entry in POST cache testStefan Roese2007-10-31-0/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix POST ethernet test for HaleakalaStefan Roese2007-10-31-7/+29
| | | | | | | | The POST ethernet test needed to be changed to dynamically determine the count of ethernet devices. This code is cloned from the 4xx ethernet driver. Signed-off-by: Stefan Roese <sr@denx.de>
* POST: Add 405EX support to 4xx UART POST testStefan Roese2007-10-31-2/+13
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* POST: limit memory test area to not touch global data anymoreYuri Tikhonov2007-08-25-0/+3
| | | | | | | | | As experienced on lwmon5, on some boards the POST memory test can corrupt the global data buffer (bd). This patch fixes this issue by checking and limiting this area. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
* POST: Fix merge problemStefan Roese2007-08-14-4/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-8/+197
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| * POST: Add option for external ethernet loopback testStefan Roese2007-08-14-1/+8
| | | | | | | | | | | | | | | | When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST is not done using an internal loopback connection, but by assuming that an external loopback connector is plugged into the board. Signed-off-by: Stefan Roese <sr@denx.de>
| * POST: Add ppc405 support to cache and UART POSTStefan Roese2007-08-14-7/+186
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | POST: Add ppc4xx UART POST support without external uart clock (lwmon5)Yuri Tikhonov2007-08-10-0/+43
| | | | | | | | | | | | | | | | The patch adds support for UART POST on ppc44x-based boards with no external serial clocks installed. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update 440EPx lwmon5 board supportStefan Roese2007-07-31-2/+12
|/ | | | | | | | - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* POST: Add ECC POST for the lwmon5 boardPavel Kolesnikov2007-07-20-0/+299
| | | | | | | | | This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* make show_boot_progress () weak.Heiko Schocher2007-07-13-6/+2
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Coding style cleanup; update CHANGELOG.Wolfgang Denk2007-07-10-9/+8
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-27/+1752
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Extend POST support for PPC440Igor Lisitsin2007-06-22-5/+572
| | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* Remove obsoleted POST files.Wolfgang Denk2007-03-19-7555/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Restructure POST directory to support of other CPUs, boards, etc.Wolfgang Denk2007-03-06-6/+7675
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* Move "ar" flags to config.mk to allow for silent "make -s"Wolfgang Denk2006-10-09-1/+1
| | | | Based on patch by Mike Frysinger, 20 Jun 2006
* Add support for a saving build objects in a separate directory.Marian Balakowicz2006-09-01-8/+10
| | | | | | | | | | | | | | | | | | | | | Modifications are based on the linux kernel approach and support two use cases: 1) Add O= to the make command line 'make O=/tmp/build all' 2) Set environement variable BUILD_DIR to point to the desired location 'export BUILD_DIR=/tmp/build' 'make' The second approach can also be used with a MAKEALL script 'export BUILD_DIR=/tmp/build' './MAKEALL' Command line 'O=' setting overrides BUILD_DIR environent variable. When none of the above methods is used the local build is performed and the object files are placed in the source directory.
* GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-18/+10
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* Cleanup for GCC-4.xWolfgang Denk2005-10-13-5/+5
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* Fix sysmon POST problem: check I2C error codesWolfgang Denk2005-07-28-2/+11
| | | | | | This fixes a problem of displaying bogus voltages when the voltages are so low that the I2C devices start failing while the rest of the system keeps running.
* Fix watchdog reset problems on LWMON boardwdenk2005-06-05-0/+1
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* * Patch by Detlev Zundel, 08 Sep 2004:wdenk2004-09-08-13/+14
| | | | | | | | | | | Update etags build target * Improve NetConsole support: add support for broadcast destination address and buffered input. * Cleanup compiler warnings for GCC 3.3.x and later * Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
* * Code cleanupwdenk2004-08-01-50/+30
| | | | | | | | | | | | | * Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)
* Patch by Pantelis Antoniou, 5 May 2004:wdenk2004-06-07-1/+62
| | | | | - Intracom board update. - Add Codec POST.
* * Patches by Pantelis Antoniou, 30 Mar 2004:wdenk2004-04-15-2/+65
| | | | | | | - add support for the Epson 156x series of graphical displays (These displays are serial and not suitable for using a normal framebuffer console on them) - add infrastructure needed in order to POST any DSPs in a board
* Patch by Pierre Aubert, 15 Mar 2004:wdenk2004-03-17-35/+19
| | | | Fix buffer overflow in IDE identification
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