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* nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-16-5/+5
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_spl: Fix cmd_ctrl usage in nand_boot.c.Scott Wood2009-07-07-7/+11
| | | | | | | | | | | | | | | | When adding large page NAND support to this file, I had a misunderstanding about the exact semantics of NAND_CTRL_CHANGE (which isn't documented anywhere I can find) -- it is apparently just a hint to drivers, which aren't required to preserve the old value for subsequent non-"change" invocations. This change makes nand_boot.c no longer assume this. Note that this happened to work by chance with some NAND drivers, which don't preserve the value, but treat 0 equivalently to NAND_CTRL_ALE. I don't have hardware to test this, so any testing is appreciated. Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_spl: read environment early, when booting from NAND using nand_splGuennadi Liakhovetski2009-07-07-0/+10
| | | | | | | | | | | | Currently, when booting from NAND using nand_spl, in the beginning the default environment is used until later in boot process the dynamic environment is read out. This way environment variables that must be interpreted early, like the baudrate or "silent", cannot be modified dynamically and remain at their default values. Fix this problem by reading out main and redundand (if used) copies of the environment in the nand_spl code. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* MX31: Add NAND SPL boot support to i.MX31 PDK board.Magnus Lilja2009-07-06-0/+91
| | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* MX31: Add NAND SPL for i.MX31.Magnus Lilja2009-06-21-0/+259
| | | | | | | | | | | | | | | | | | This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov <scn1874@yandex.ru> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Fix e-mail address of Gary Jennejohn.Detlev Zundel2009-05-15-1/+1
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* SIMPC8313 board: fix out of tree building.Wolfgang Denk2009-03-09-9/+18
| | | | | | | | | Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2009-01-28-2/+0
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| * nand_spl: Fix compile problem with board_nand_init() prototypeStefan Roese2009-01-26-2/+0
| | | | | | | | | | | | | | | | This patch removes the now obsolete and additionally wrongly defined board_nand_init() prototype from nand_spl/nand_boot.c. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 buildKim Phillips2009-01-28-1/+5
|/ | | | | | | | | | | | | | extend commit c70564e6b1bd08f3230182392238907f3531a87e "NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency to the simpc8313 build and fix this: ...Large Page NAND...Configuring for SIMPC8313 board... nand_boot_fsl_elbc.o: In function `nand_boot': nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache' make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1 make: *** [nand_spl] Error 2 Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'next'Kim Phillips2009-01-23-0/+152
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| * mpc83xx: New board support for SIMPC8313Ron Madrid2009-01-23-0/+152
| | | | | | | | | | | | | | | | | | | | | | This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | NAND: Fix cache and memory inconsistency issueDave Liu2009-01-23-1/+10
|/ | | | | | | | | | | | | | | | | | We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-1/+6
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-2/+2
| | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-42/+42
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ARM: Add support for S3C6400 based SMDK6400 boardGuennadi Liakhovetski2008-08-31-0/+207
| | | | | | | | | SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl driver for it too. The board can also boot from the NOR flash, but due to hardware limitations it can only address 64KiB on it, which is not enough for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* NAND: Remove delay from nand_boot_fsl_elbc.c.Scott Wood2008-08-21-2/+0
| | | | | | It was for debugging purposes, and shouldn't have been left in. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-08-14-3/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* nand_spl: Support page-aligned read in nand_load, use chipselectGuennadi Liakhovetski2008-08-12-10/+20
| | | | | | | | | Supporting page-aligned reads doesn't incure any sinificant overhead, just a small change in the algorithm. Also replace in_8 with readb, since there is no in_8 on ARM. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND boot: Update large page support for current API.Scott Wood2008-08-12-30/+20
| | | | | | | Also, remove the ctrl variable in favor of passing the constants directly, and remove redundant (u8) casts. Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND boot: MPC8313ERDB supportScott Wood2008-08-12-2/+305
| | | | | | | | | Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Update nand_spl driver to match updated nand subsystemStefan Roese2008-08-12-15/+19
| | | | | | | | | This patch changes the NAND booting driver nand_spl/nand_boot.c to match the new infrastructure from the updated NAND subsystem. This NAND subsystem was recently synced again with the Linux 2.6.22 MTD/NAND subsystem. Signed-off-by: Stefan Roese <sr@denx.de>
* NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile.Scott Wood2008-07-30-1/+1
| | | | | | This fixes building out-of-tree. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-3/+3
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Fix problem with SDRAM init in bamboo NAND booting portStefan Roese2008-06-04-8/+2
| | | | | | | | | | | | | This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) introduced by the commit: ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S With this patch SDRAM will get initialized again and booting from NAND is working again. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
* Remove shell variable UNDEF_SYM.Kenneth Johansson2008-06-03-5/+5
| | | | | | | UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
* ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese2008-06-03-14/+13
| | | | | | | | | | | This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.SStefan Roese2008-06-03-6/+5
| | | | | | | | | | | | | | | | | This patch consolidates the 405 and 440 parts of the NAND booting code selected via CONFIG_NAND_SPL. Now common code is used to initialize the SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. Only *after* running from this location, nand_boot() is called. Please note that the initsdram() call is now moved from nand_boot.c to start.S. I experienced problems with some boards like Kilauea (405EX), which don't have internal SRAM (OCM) and relocation needs to be done to SDRAM before the NAND controller can get accessed. When initdram() is called later on in nand_boot(), this can lead to problems with variables in the bss sections like nand_ecc_pos[]. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand buildStefan Roese2008-05-14-1/+7
| | | | | | | | Canyonlands has a file ddr2_fixed.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM moduleStefan Roese2008-04-30-5/+7
| | | | | | | | | | This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-nand-flashWolfgang Denk2008-04-25-1/+63
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| * nand_spl: Update nand_spl to support 2k page size NAND devicesStefan Roese2008-04-18-1/+63
| | | | | | | | | | | | | | | | | | This patch adds support for booting from 2k page sized NAND device (e.g. Micron 29F2G08AAC). Tested on AMCC Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese2008-04-18-3/+3
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMMStefan Roese2008-04-18-4/+4
|/ | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-0/+315
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-4/+4
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* fix various commentsMarcel Ziswiler2008-01-09-1/+1
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* fix comments with new drivers organizationMarcel Ziswiler2008-01-09-3/+3
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* ppc4xx: Fix Sequoia NAND booting targetStefan Roese2008-01-04-1/+5
| | | | | | | The Sequoia NAND booting target now uses the recently extracted cpu/ppc4xx/denali_data_eye.c file too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation problem of kilauea/haleakala nand booting targetStefan Roese2007-12-28-1/+1
| | | | | | | Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge commit 'u-boot/master' into for-1.3.1Stefan Roese2007-12-11-3/+3
|\ | | | | | | | | | | Conflicts: drivers/rtc/Makefile
| * drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD2007-11-25-3/+3
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese2007-11-03-0/+219
| | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix acadia_nand build problemStefan Roese2007-10-31-1/+5
| | | | | | | | | | | | | | Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAMEugene O'Brien2007-10-31-0/+6
|/ | | | | | | | | | | | | This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Individual handling of sdram.c for bamboo_nand buildGrzegorz Bernacki2007-09-11-0/+6
| | | | | | | | Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-5/+15
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-0/+214
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
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