summaryrefslogtreecommitdiff
path: root/nand_spl/board/amcc
Commit message (Collapse)AuthorAgeLines
* ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM'sStefan Roese2009-07-30-14/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Canyonlands boards are equipped with different SODIMM's. This is no problem with the "normal" NOR booting Canyonlands U-Boot, since it automatically detects the SODIMM's via SPD data and correctly configures them. But the NAND booting version is different. Here we only have 4k of image size to completely setup the hardware, including DDR2 setup. So we need to use a fixed DDR2 setup here. This doesn't work for different SODIMM's right now. Currently only this Crucial SODIMM is support: CT6464AC667.8FB (dual ranked) Now some boards are shipped with this SODIMM: CT6464AC667.4FE (single ranked) This patch now supports both SODIMM's by configuring first for the dual ranked DIMM. A quick shows, if this module is really installed. If this test fails, the DDR2 controller is re-configured for the single ranked SODIMM. Tested with those SODIMM's: CT6464AC667.8FB (dual ranked) CT6464AC667.4FE (single ranked) Signed-off-by: Stefan Roese <sr@denx.de>
* nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-16-5/+5
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+5
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-7/+7
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Fix merge problemsStefan Roese2008-08-06-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-3/+3
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Fix problem with SDRAM init in bamboo NAND booting portStefan Roese2008-06-04-8/+2
| | | | | | | | | | | | | This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) introduced by the commit: ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S With this patch SDRAM will get initialized again and booting from NAND is working again. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
* Remove shell variable UNDEF_SYM.Kenneth Johansson2008-06-03-5/+5
| | | | | | | UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
* ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese2008-06-03-14/+13
| | | | | | | | | | | This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand buildStefan Roese2008-05-14-1/+7
| | | | | | | | Canyonlands has a file ddr2_fixed.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM moduleStefan Roese2008-04-30-5/+7
| | | | | | | | | | This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese2008-04-18-3/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMMStefan Roese2008-04-18-4/+4
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-0/+315
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-4/+4
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* fix comments with new drivers organizationMarcel Ziswiler2008-01-09-3/+3
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* ppc4xx: Fix Sequoia NAND booting targetStefan Roese2008-01-04-1/+5
| | | | | | | The Sequoia NAND booting target now uses the recently extracted cpu/ppc4xx/denali_data_eye.c file too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation problem of kilauea/haleakala nand booting targetStefan Roese2007-12-28-1/+1
| | | | | | | Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge commit 'u-boot/master' into for-1.3.1Stefan Roese2007-12-11-3/+3
|\ | | | | | | | | | | Conflicts: drivers/rtc/Makefile
| * drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD2007-11-25-3/+3
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese2007-11-03-0/+219
| | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix acadia_nand build problemStefan Roese2007-10-31-1/+5
| | | | | | | | | | | | | | Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAMEugene O'Brien2007-10-31-0/+6
|/ | | | | | | | | | | | | This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Individual handling of sdram.c for bamboo_nand buildGrzegorz Bernacki2007-09-11-0/+6
| | | | | | | | Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-5/+15
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-0/+214
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-2/+313
|\
| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-5/+6
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese2007-06-01-0/+306
| | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese2007-05-05-5/+1
|/ | | | | | | | Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-1/+5
| | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-0/+2
| | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix sequoia separate object direcory building problems.Marian Balakowicz2006-10-23-24/+40
|
* Update NAND boot documentationStefan Roese2006-09-12-2/+2
| | | | Patch by Stefan Roese, 12 Sep 2006
* Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-0/+197
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
generated by cgit v1.1 at 2024-12-27 06:28:43 +0000