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* dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-10-3/+0
| | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+1
| | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-0/+1
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pmic: max77686 set the same compatible as in the kernelPrzemyslaw Marczak2015-05-14-1/+1
| | | | | | | This commit also updates the proper dts files. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* tpm: Rename Infineon TPM to slb9645ttSimon Glass2015-05-14-1/+1
| | | | | | This name is used in Linux, so use it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: video: Support serial output resource (SOR) on tegra124Simon Glass2015-05-13-0/+3
| | | | | | | | | The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add binding decode function for display-timingsSimon Glass2015-05-13-0/+92
| | | | | | | | This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: usb: exynos: Drop legacy USB codeSimon Glass2015-05-06-2/+0
| | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Rename setup_fdt() and make it prepare alsoSimon Glass2015-04-23-2/+2
| | | | | | | There is little reason to split these two functions. Bring them together which simplifies the init sequence. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: sandbox: Move setup code from board_f to fdtdecSimon Glass2015-04-23-0/+31
| | | | | | | We want to be able to set up the device tree in SPL, so move this code to a common place. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add a panic_str() function to reduce code sizeSimon Glass2015-04-23-3/+5
| | | | | | | | The printf() in panic() adds about 1.5KB of code size to SPL when compiled with Thumb-2. Provide a smaller version that does not support printf()-style arguments and use it in two commonly compiled places. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: exynos: Match up device tree with kernel versionSimon Glass2015-04-18-1/+0
| | | | | | | | | | | The U-Boot device trees are slightly different in a few places. Adjust them to remove most of the differences. Note that U-Boot does not support the concept of interrupts as distinct from GPIOs, so this difference remains. For sandbox, use the same keyboard file as for ARM boards and drop the host emulation bus which seems redundant. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Drop LPC compatible string in fdtdecSimon Glass2015-04-18-1/+0
| | | | | | | This is not needed now that we have moved chromebook_link and cros_ec to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: cros_ec: Drop compatible string in fdtdecSimon Glass2015-04-18-1/+0
| | | | | | This is not needed now that we have moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-1/+2
| | | | | | | | | | | | The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-1/+1
| | | | | | | | | | | | | | | | Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Tighten up error handling in fdtdec_get_pci_addr()Simon Glass2015-04-16-1/+3
| | | | | | | | | | | | | This function returns -ENOENT when the property is missing (which the caller might forgive) and also when the property is present but incorrectly formatted (which many callers would like to report). Update the error return value to allow these different situations to be distinguished. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* fdt: Export fdtdec_get_number() for general useSimon Glass2015-04-16-1/+1
| | | | | | | This function is missing a prototype but is more widey useful. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: UniPhier: adjust device trees for business transferMasahiro Yamada2015-03-15-1/+1
| | | | | | | Panasonic's System LSI products, UniPhier SoC family, have been transferred to Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* usb: UniPhier: add UniPhier on-chip xHCI host driver supportMasahiro Yamada2015-03-01-0/+1
| | | | | | | Support xHCI host driver used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* fdtdec: Add compatible id and string for Intel Quark MRCBin Meng2015-02-06-0/+1
| | | | | | | | Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Drop unused COMPAT features for SPISimon Glass2015-01-29-1/+0
| | | | | | | This has moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: tegra: Drop unused COMPAT features for I2C, SPISimon Glass2015-01-29-6/+0
| | | | | | These have moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Drop gpio.h header from fdtdec.cSimon Glass2015-01-29-2/+0
| | | | | | | Since GPIO support has now moved to the driver model uclass, we can drop this include. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Remove the old GPIO functionsSimon Glass2015-01-29-95/+0
| | | | | | | Now that we support device tree GPIO bindings directly in the driver model GPIO uclass we can remove these functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Add a function to decode phandles with argumentsSimon Glass2015-01-29-0/+124
| | | | | | | | | | | For GPIOs and other functions we want to look up a phandle and then decode a list of arguments for that phandle. Each phandle can have a different number of arguments, specified by a property in the target node. This is the "#gpio-cells" property for GPIOs. Add a function to provide this feature, taken modified from Linux 3.18. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+1
| | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add several apis to decode pci device nodeBin Meng2015-01-13-14/+157
| | | | | | | | | | | | | | This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
* pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+3
| | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+1
| | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* power: Add AMS AS3722 PMIC supportThierry Reding2014-12-18-0/+1
| | | | | | | | | The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2014-12-01-15/+0
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| * fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada2014-11-27-15/+0
| | | | | | | | | | | | | | | | | | | | The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-01-0/+3
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| * x86: Add initial video device init for Intel GMASimon Glass2014-11-25-0/+1
| | | | | | | | | | | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2014-11-26-7/+81
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| * fdt: Add a function to decode a named memory regionSimon Glass2014-11-21-0/+61
| | | | | | | | | | | | | | | | Permit decoding of a named memory region from the device tree. This allows easy run-time configuration of the address of on-chip SRAM, SDRAM, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * fdt: Enhance flashmap function to deal with region propertiesSimon Glass2014-11-21-0/+8
| | | | | | | | | | | | | | | | | | Flash regions can optionally be compressed or hashed. Add the ability to read this information from the flashmap. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
| * fdt: Use the correct return types for fdtdec_decode_region()Simon Glass2014-11-21-7/+12
| | | | | | | | | | | | | | | | Use the correct FDT data types for this function. Also add more debugging. Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-3/+3
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | dm: fdt: Correct handling of aliases with embedded digitsSimon Glass2014-11-22-3/+3
| |/ | | | | | | | | | | | | | | | | | | Since we scan from left to right looking for the first digit, "i2c0" returns 2 instead of 0 for the alias number. Adjust the code to scan from right to left instead. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* | x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | fdt: Add a function to decode a variable-sized u32 arraySimon Glass2014-11-21-0/+20
|/ | | | | | | Sometimes an array can be of variable size up to a maximum. Add a helper function to decode this. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-10-23-0/+1
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| * x86: dts: Add device tree compatible string for Intel IPCSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | Add this to the table so that it can be recognised. Signed-off-by: Simon Glass <sjg@chromium.org>
* | fdt: Add a function to return PCI BDF tripletThierry Reding2014-10-22-0/+14
| | | | | | | | | | | | | | | | | | The fdtdec_pci_get_bdf() function returns the bus, device, function triplet of a PCI device by parsing the "reg" property according to the PCI device tree binding. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | fdt: Add resource parsing functionsThierry Reding2014-10-22-0/+57
|/ | | | | | | | | Add the fdt_get_resource() and fdt_get_named_resource() functions which can be used to parse resources (memory regions) from an FDT. A helper to compute the size of a region is also provided. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
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