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* lpc32xx: devkit3250: add spl build supportVladimir Zapolskiy2015-08-12-0/+53
| | | | | | | | | | | | The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: devkit3250: update of board configurationVladimir Zapolskiy2015-08-12-5/+87
| | | | | | | | | | | | This change adds more peripherals to Timll DevKit3250 board, namely MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C. Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* arm, at91: support for sam9260 based smartweb boardHeiko Schocher2015-08-12-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the at91sam9260 based board smartweb from siemens. SPL is used without serial support, as this SoC has only 4k sram for running SPL. Here a U-Boot bootlog: RomBOOT > U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200) CPU: AT91SAM9260 Crystal frequency: 18.432 MHz CPU clock : 198.656 MHz Master clock : 99.328 MHz Watchdog enabled DRAM: 64 MiB WARNING: Caches not enabled NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Heiko Schocher <hs@denx.de>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-0/+11
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* port vexpress to use distro boot commandsDennis Gilmore2015-08-12-17/+17
| | | | | | | | remove options defined in the distro defaults add distro bot commands set scriptaddr value Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Move setting CONFIG_BOOTP_VCI_STRING to before including the vexpress-common ↵Dennis Gilmore2015-08-12-3/+3
| | | | | | header Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* PXE: if a board has set its own value for CONFIG_BOOTP_VCI_STRING do not set ↵Dennis Gilmore2015-08-12-0/+6
| | | | | | the default one. Use the board set value instead Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* ARM: highbank: remove DRAM bank setupRob Herring2015-08-12-1/+2
| | | | | | | | | | | On the highbank platform the SoC's management controller firmware will probe the DRAM modules and populates the initial device tree with the correct values. Therefore the memory sizes in the DT are already correct, so remove U-Boot's DRAM bank setup so the memory node is not "fixed up" by u-boot. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* power: regulator: add pfuze100 supportPeng Fan2015-08-12-4/+20
| | | | | | | | | | | | | 1. Add new regulator driver pfuze100. * Introduce struct pfuze100_regulator_desc for maintaining info for one regulator. 2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100. 3. This driver intends to support PF100, PF200 and PF3000. 4. Add related macro definition in pfuze header file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
* power: regulator: update comments for regulator-namePeng Fan2015-08-12-0/+1
| | | | | | | | | | We do not need that "regulator-name" property must be provided in dts. If "regulator-name" property is not provided in dts, node name will chosen for settings '.name' field of uc_pdata. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
* power: pfuze100 correct SWBST macro definitionPeng Fan2015-08-12-4/+4
| | | | | | | | | | According to datasheet, SWBST_MODE starts from bit 2 and it occupies 2 bits. So SWBST_MODE_MASK should be 0xC, and SWBST_MODE_xx should be ([mode] << 2). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-08-0/+12
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| * sunxi: Do not add a stdout-path alias to dts on boards without a serial portHans de Goede2015-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not add a bogus (pointing to a non existing serial port) stdout-path alias to dts on boards without a serial port. Note that we still define CONS_INDEX as this is used by the SPL where we do not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored. We are getting away with this because the sun5i die actually has an uart0, which in the A13 package is not routed to the outside, so we are simply sending SPL bootup messages to the tx pin at the edge of the die, and they go no further from there... And sofar we only have one A13 board which does not have a serial port, all others do have a serial port. This kinda makes sense since the A13 is a much lower pincount package compared to all the other sunxi SoCs. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-08-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD usefulMarek Vasut2015-08-08-0/+4
| | | | | | | | | | | | | | | | Enable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Fix LOADADDRMarek Vasut2015-08-08-2/+2
| | | | | | | | | | | | | | | | | | Setting LOADADDR to 0x8000 is a bad idea, it is very likely that some kind of overlap will happen. Move the LOADADDR 0x01000000 (16MiB from start of RAM) to make sure no overlap happens when loading kernel for example. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Enable CONFIG_SPI_FLASH_BARMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | This is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL buildMarek Vasut2015-08-08-0/+2
| | | | | | | | | | | | | | We do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Zap incorrect config optionsMarek Vasut2015-08-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option. Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-6/+8
| | | | | | | | | | | | | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-2/+1
| | | | | | | | | | | | | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-0/+9
| | | | | | | | | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+14
| | | | | | | | | | | | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-3/+0
| | | | | | | | | | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-1/+0
| | | | | | | | | | | | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: enable the Altera SDRAM controller driverDinh Nguyen2015-08-08-0/+5
| | | | | | | | | | | | | | Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-6/+6
|/ | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-264/+771
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| * dm: core: Fix a typo in the uclass_get_device_by_name() commentSimon Glass2015-08-06-1/+1
| | | | | | | | | | | | | | This function comment has a typo. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: core: Add a way to set a device nameSimon Glass2015-08-06-0/+15
| | | | | | | | | | | | | | | | | | | | Some devices are bound entirely by probing and do not have the benefit of a device tree to give them a name. This is very common with PCI and USB. In most cases this is fine, but we should add an official way to set a device name. This should be called in the device's bind() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * devres: add debug command to dump device resourcesMasahiro Yamada2015-08-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new command can dump all device resources associated to each device. The fields in every line shows: - The address of the resource - The size of the resource - The name of the release function - The stage in which the resource has been acquired (BIND/PROBE) Currently, there is no driver using devres, but if such drivers are implemented, the output of this command should look like this: => dm devres - root_driver - soc - extbus - serial@54006800 bfb541e8 (8 byte) devm_kmalloc_release BIND bfb54440 (4 byte) devm_kmalloc_release PROBE bfb54460 (4 byte) devm_kmalloc_release PROBE - serial@54006900 bfb54270 (8 byte) devm_kmalloc_release BIND - gpio@55000000 - i2c@58780000 bfb5bce8 (12 byte) devm_kmalloc_release PROBE bfb5bd10 (4 byte) devm_kmalloc_release PROBE - eeprom bfb54418 (12 byte) devm_kmalloc_release BIND Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: make Devres optional with CONFIG_DEVRESMasahiro Yamada2015-08-06-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Devres requires additional 16 byte for each allocation, which is not so insignificant in some cases. Add CONFIG_DEVRES to make this framework optional. If the option is disabled, devres functions fall back to non-managed variants. For example, devres_alloc() to kzalloc(), devm_kmalloc() to kmalloc(), etc. Because devres_head is also surrounded by an ifdef conditional, there is no memory overhead when CONFIG_DEVRES is disabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: add devm_kmalloc() and friends (managed memory allocators)Masahiro Yamada2015-08-06-0/+44
| | | | | | | | | | | | | | | | | | | | | | devm_kmalloc() is identical to kmalloc() except that the memory allocated with it is managed and will be automatically released when the device is removed/unbound. Likewise for the other variants. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * devres: introduce Devres (Managed Device Resource) frameworkMasahiro Yamada2015-08-06-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In U-Boot's driver model, memory is basically allocated and freed in the core framework. So, low level drivers generally only have to specify the size of needed memory with .priv_auto_alloc_size, .platdata_auto_alloc_size, etc. Nevertheless, some drivers still need to allocate/free memory on their own in case they cannot statically know the necessary memory size. So, I believe it is reasonable enough to port Devres into U-boot. Devres, which originates in Linux, manages device resources for each device and automatically releases them on driver detach. With devres, device resources are guaranteed to be freed whether initialization fails half-way or the device gets detached. The basic idea is totally the same to that of Linux, but I tweaked it a bit so that it fits in U-Boot's driver model. In U-Boot, drivers are activated in two steps: binding and probing. Binding puts a driver and a device together. It is just data manipulation on the system memory, so nothing has happened on the hardware device at this moment. When the device is really used, it is probed. Probing initializes the real hardware device to make it really ready for use. So, the resources acquired during the probing process must be freed when the device is removed. Likewise, what has been allocated in binding should be released when the device is unbound. The struct devres has a member "probe" to remember when the resource was allocated. CONFIG_DEBUG_DEVRES is also supported for easier debugging. If enabled, debug messages are printed each time a resource is allocated/freed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: add DM_FLAG_BOUND flagMasahiro Yamada2015-08-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Currently, we only have DM_FLAG_ACTIVATED to indicate the device status, but we still cannot know in which stage is in progress, binding or probing. This commit introduces a new flag, DM_FLAG_BOUND, which is set when the device is really bound, and cleared when it is unbound. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: Support address translation for simple-busSimon Glass2015-08-06-0/+12
| | | | | | | | | | | | | | | | The 'ranges' property can be used to specify a translation from the system address to the bus address. Add support for this using the dev_get_addr() function, which devices should use to find their address. Signed-off-by: Simon Glass <sjg@chromium.org>
| * lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedefYork Sun2015-08-06-4/+2
| | | | | | | | | | | | | | | | | | fdt_addr_t is a physical address. It can be either 64-bit or 32-bit, depending on the architecture. It should be phys_addr_t instead of u64 or u32. Similarly, fdt_size_t is changed to phys_size_t. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
| * exynos: Add support for springSimon Glass2015-08-05-0/+20
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: Drop unused compatible ID for the NXP video bridgeSimon Glass2015-08-05-1/+0
| | | | | | | | | | | | This has moved to driver model so we can drop the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org>
| * video: Remove the old parade driverSimon Glass2015-08-05-23/+0
| | | | | | | | | | | | | | We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Remove the old tunnel codeSimon Glass2015-08-05-14/+0
| | | | | | | | | | | | This is not needed with driver mode. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * power: Remove old TPS65090 driversSimon Glass2015-08-05-76/+0
| | | | | | | | | | | | | | Remove the old drivers (both the normal one and the cros_ec one) now that we have new drivers that use driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5250-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | Now that most exynos5250 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5420-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | | | Now that exynos5420 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: config: Move common options to the common headers and tidy upSimon Glass2015-08-05-90/+39
| | | | | | | | | | | | | | | | | | | | Many options are duplicated on the exynos5 boards. Move these to the common files. Also some options are not used so can be removed. Tidy this up to make the files easier to maintain. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
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