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* [Blackfin][PATCH] code cleanupAubrey Li2007-03-12-1/+1
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* [Blackfin][PATCH] code cleanupAubrey Li2007-03-10-362/+337
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* [Blackfin][PATCH-2/2] Common files changed to support bf533 platformAubrey.Li2007-03-09-1/+1
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* [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform ↵Aubrey.Li2007-03-09-1333/+1707
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* Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-03-08-2374/+2858
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| * mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala2007-03-02-40/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: update [local-]mac-address properties on UEC based devicesKim Phillips2007-03-02-0/+2
| | | | | | | | | | | | | | 8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: add command line editing by defaultKim Phillips2007-03-02-0/+4
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| * mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDSXie Xiaobo2007-03-02-4/+31
| | | | | | | | | | | | | | MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo2007-03-02-10/+47
| | | | | | | | | | | | | | MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
| * mpc83xx: Add support for the MPC8349E-mITX-GPTimur Tabi2007-03-02-280/+220
| | | | | | | | | | | | | | | | Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi <timur@freescale.com>
| * mpc83xx: Fix the LAW1/3 bugDave Liu2007-03-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | The patch solves the alignment problem of the local bus access windows to render accessible the memory bank and PHY registers of UPC 1 (starting at 0xf801 0000). What we actually did was to adjust the sizes of the bus access windows so that the base address alignment requirement would be met. Signed-off-by: Chereji Marian <marian.chereji@freescale.com> Signed-off-by: Gridish Shlomi <gridish@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: make 8360 default environment fdt be 8360 (not 8349)Kim Phillips2007-03-02-1/+1
| | | | | | | | make 8360 default environment fdt be 8360 (not 8349)
| * mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala2007-03-02-10/+10
| | | | | | | | | | | | | | | | The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+744
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
| * mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-13/+720
| | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-2047/+1108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* | Minor cleanupWolfgang Denk2007-03-08-1/+1
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* | Merge with /home/hs/jupiter/u-bootWolfgang Denk2007-03-08-0/+277
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| * | [PATCH] Added support for the jupiter board.Heiko Schocher2007-02-16-0/+277
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-21/+37
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| * \ \ Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-21/+37
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| | * | | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | [PATCH] Update AMCC Yucca 440SPe eval board supportStefan Roese2007-03-08-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Small AMCC Katmai 440SPe updateStefan Roese2007-03-08-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-1/+24
| | | |/ | | |/| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-1/+2
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| * | | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval boardStefan Roese2007-03-07-1/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | | HMI1001: fix build error, cleanup compiler warnings.Wolfgang Denk2007-03-07-0/+1
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* | | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-8/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx-merge-srStefan Roese2007-03-01-1/+1
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| * \ Merge with /home/sr/git/u-boot/denxStefan Roese2007-03-01-1/+1
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| | * | SC3: fix typo in default environmentWolfgang Denk2007-02-28-1/+1
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* | | | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-31/+39
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| * | | [PATCH] I2C: Add missing default CFG_RTC_BUS_NUM & CFG_DTT_BUS_NUMStefan Roese2007-03-01-0/+8
| |/ / | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | Minor code cleanup.Wolfgang Denk2007-02-27-31/+30
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| * | MCC200 update - add LCD Progress IndicatorSergei Poselenov2007-02-27-0/+1
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* | | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-6/+21
|/ / | | | | | | | | | | | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH v3] Add sync to ensure flash_write_cmd is fully finishedHaiying Wang2007-02-21-4/+50
| | | | | | | | | | | | | | | | | | Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command is fully finished. The sync() is defined in each CPU's io.h file. For those CPUs which do not need sync for now, a dummy sync() is defined in their io.h as well. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-02-20-6/+334
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| * | [PATCH 9_9] Use "void *" not "unsigned long *" for block dev read_write ↵Grant Likely2007-02-20-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | buffer pointers Block device read/write is anonymous data; there is no need to use a typed pointer. void * is fine. Also add a hook for block_read functions Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | [PATCH 8_9] Add block_write hook to block_dev_desc_tGrant Likely2007-02-20-0/+4
| | | | | | | | | | | | | | | | | | Preparation for future patches which support block device writing Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | [PATCH 3_9] Move buffer print code from md command to common functionGrant Likely2007-02-20-0/+2
| | | | | | | | | | | | | | | | | | | | | Printing a buffer is a darn useful thing. Move the buffer print code into print_buffer() in lib_generic/ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | [PATCH 1_4] Merge common get_dev() routines for block devicesGrant Likely2007-02-20-3/+12
| | | | | | | | | | | | | | | | | | | | | Each of the filesystem drivers duplicate the get_dev routine. This change merges them into a single function in part.c Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | [PATCH] Update Sequoia EBC configuration (NOR FLASH)Stefan Roese2007-02-19-2/+2
| | | | | | | | | | | | | | | | | | | | | As spotted by Matthias Fuchs, the READY input should not be enabled for the NOR FLASH on the Sequoia board. Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-02-16-0/+305
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| | * [Motion-PRO] Preliminary support for the Motion-PRO board.Bartlomiej Sieka2007-02-09-0/+305
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| * | [PATCH] Update some AMCC 4xx board config files (set initrd_high)Stefan Roese2007-02-07-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some boards that can have more than 768MBytes of SDRAM need to set "initrd_high", so that the initrd can be accessed by the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-2/+423
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-42/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-09 14:24:53 +0000