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| * | | powerpc: t1040qds: Use generic ethsw commandsCodrin Ciubotariu2016-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commands for the VSC9953 l2 switch from T1040 became generic in patch https://patchwork.ozlabs.org/patch/499748/ and the define was renamed. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-21/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | | | armv8: ls1043a: load Fman ucode from SD/MMC under SD bootQianyu Gong2016-04-06-1/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8: ls1043a: load Fman ucode from NAND flash under NAND bootQianyu Gong2016-04-06-1/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8/ls1043aqds: modify CONFIG_SYS_MAX_FLASH_BANKS to 1Wenbin Song2016-04-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is only one flash bank for ls1043aqds. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | fsl: esdhc: consolidate fsl_esdhc_cfg structurePeng Fan2016-04-06-5/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can use phys_addr_to for esdhc_base to discard the #ifdef. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-04-04-23/+45
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| * | | ARM64: zynqmp: Enable EFI partition supportMichal Simek2016-04-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable EFI partition support for ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add uEnv.txt supportMichal Simek2016-04-04-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is executed after load of uEnv.txt if it is defined in the uEnv.txt env text file. The default importbootenv macro reads the uEnv.txt from mmc. Additional to this, usb_loadbootenv is added to support loading uEnv.txt from usb dev 0. Signed-off-by: Jason Wu <jason.wu.misc@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | block: Add support for Ceva sataMichal Simek2016-04-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial Ceva Sata init code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | ARM64: zynqmp: Read RAM information from DTMichal Simek2016-04-04-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read information about memory from DT. This patch simplify life with synchronization between DT and board files. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: Move HUSH enabling from board file to defconfigMichal Simek2016-04-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Simplify board config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable FAT write and EXT4 write for USB tooMichal Simek2016-04-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Enabling writing files to FAT and EXT4 for USB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Decrease boot delaySoren Brinkmann2016-04-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize it with zynq platform. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Remove !OF_CONTROL code for timer and interruptMichal Simek2016-04-04-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: zybo: Enabling reading MAC address from EEPROMMichal Simek2016-04-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Zybo has on board I2C EEPROM which contains preprogrammed MAC address. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Enable option to overwrite default variablesMichal Simek2016-04-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable overwriting variables out of main config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | zynq-common: Enable phy driver for Xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of Xilinx PCS/PMA core phy for Zynq Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: mvebu: Add basic support for Armada 375 eval board db-88f6720Stefan Roese2016-04-04-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell A375 eval board. Tested are the following interfaces: - I2C - SPI - SPI NOR - Ethernet (mvpp2), port 0 & 1 Currently the A375 SerDes and DDR3 init code is not intergrated. So the SPL U-Boot is not fully functional. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | | dt-bindings: Add include/dt-bindings/phy/phy.h from Linux v4.4Stefan Roese2016-04-04-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be needed by the upcoming Marvell Armada 375 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | | net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375Stefan Roese2016-04-04-0/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the mvpp2 ethernet controller which is integrated in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4), which has been stripped of the in U-Boot unused portions. Tested on the Marvell Armada 375 eval board db-88f6720. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
* | | drivers: block: add block device cacheEric Nelson2016-04-01-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com>
* | | board: Add Qualcomm Dragonboard 410C supportMateusz Kulikowski2016-04-01-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-01-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | ehci-ci.h: drop generic USBCMD fieldsMateusz Kulikowski2016-04-01-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Use definitions from ehci.h instead. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* | | usb: ehci-ci: Add missing registers.Mateusz Kulikowski2016-04-01-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some registers of usb_ehci were marked as reserved. This may be true for some variants of Chipidea USB core, but they have meaning on other devices. The following registers were added: sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* | | usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* | | usb: ulpi: Fix compile warning in read/write on 64-bit machines.Mateusz Kulikowski2016-04-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32. This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit. It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing. This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | | usb: ulpi: Fix viewport_addr typeMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices. This fix changes its type to match pointer size. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | | Migrate CONFIG_ULPI* to KconfigMateusz Kulikowski2016-04-01-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly. Affected boards: colibri_t20, harmony, mcx, mt_ventoux, twister, zynq_(picozed, zc702, zc706, zed, zybo) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | board: ti: DRA7: Add DP83867 TI phy for rev cDan Murphy2016-04-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | kc1: Add some sysboot and devicetree-related environment variablesPaul Kocialkowski2016-04-01-0/+2
| | | | | | | | | | | | | | | | | | This adds some environment variables for sysboot and devicetree. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | kc1: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | sniper: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | configs: ti_armv7_keystone2: make SYS_TEXT_BASE configurable at build timeVitaly Andrianov2016-04-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot for general purpose KS2 devices is loaded to the beginning of the internal memory (0x0c000000). Secure devices uses this memory and CONFIG_SYS_TEXT_BASE has to be different for those devices. This commit make this configurable at build time by giving CONFIG_SYS_TEXT_BASE as a command line definition to make command. Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
* | | rpi: BCM2837 and Raspberry Pi 3 32-bit supportStephen Warren2016-04-01-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with the CPU complex swapped out for a quad-core ARMv8. This can operate in 32- or 64-bit mode. 32-bit mode is the current default selected by the VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of U-Boot for the Raspberry Pi 3. >From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a change in usage of the SoC UARTs. On all previous Pis, the PL011 was the only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a UART to connect to the SoC. By default, the PL011 is used for this purpose since it has larger FIFOs than the other "mini" UART. However, this can be configured via the VideoCore firmware's config.txt file. This patch hard-codes use of the mini UART in the RPi 3 port. If your system uses the PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot port instead. A future change might determine which UART to use at run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed together. The mini UART has some limitations. One externally visible issue in the BCM2837 integration is that the UART divides the SoC's "core clock" to generate the baud rate. The core clock is typically variable, and under control of the VideoCore firmware for thermal management reasons. If the VC FW does modify the core clock rate, UART communication will be corrupted since the baud rate will vary from the expected value. This was not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To work around this, the VideoCore firmware can be told not to modify the SoC core clock. However, the only way this can happen and be thermally safe is to limit the core clock to a low/minimum frequency. This leaves performance on the table for use-cases that don't care about a UART console. Consequently, use of the mini UART console must be explicitly requested by entering the following line into config.txt: enable_uart=1 A recent version of the VC firmware is required to ensure that the mini UART is fully and correctly initialized by the VC FW; at least firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: bcm2835: move CONFIG_BCM283* to KconfigStephen Warren2016-04-01-2/+0
| | | | | | | | | | | | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Drop command-processing code when CONFIG_CMDLINE is disabledSimon Glass2016-04-01-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Command parsing and processing code is not needed when the command line is disabled. Remove this code in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-04-01-13/+57
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| * | | sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-01-6/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: usb_phy: Add support for A83T USB PHYsChen-Yu Tsai2016-03-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | power: axp818: Add support for FLDOsChen-Yu Tsai2016-03-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: axp: Support VBUS drive GPIO on AXP818Chen-Yu Tsai2016-03-31-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AXP818 supports VBUS drive function, even though the manual does not mention it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: axp: Generalize register macros for VBUS drive GPIOChen-Yu Tsai2016-03-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | power: axp818: Remove undefined axp818_init()Chen-Yu Tsai2016-03-31-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | axp818_init() is declared, but never defined. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | ARM: uniphier: remove CONFIG_ARP_TIMEOUT defineMasahiro Yamada2016-04-01-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I no longer see the problem claimed in the comment block. Rather, the 0.5 msec timeout seems too short for some TFTP servers. Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | ARM: uniphier: drop unneeded defines related to legacy serial driverMasahiro Yamada2016-04-01-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These defined were used for pre-DM ns16550 serial driver. They are unneeded because UniPhier SoCs now use DM serial. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | ARM: uniphier: add sramupdate commandMasahiro Yamada2016-04-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This command would be useful to update U-Boot images in SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | ARM: uniphier: make u-boot-with-spl.bin really availableMasahiro Yamada2016-04-01-0/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image") claimed that u-boot-with-spl.bin would be useful in its commit log, but it was not available because the commit missed to define CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined either (see include/config_fallbacks.h). So, the SPL image is not padded correctly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-05 10:41:19 +0000