| Commit message (Collapse) | Author | Age | Lines |
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Convert ext2/4 load, ls, and write functions to use common device and
partition parsing function. With the common function "dev:part" can come
from the environment and a '-' can be used in that case.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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There's no real need to expose this and it can be removed by using a static
allocation.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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All block device related commands (scsiboot, fatload, ext2ls, etc.) have
simliar duplicated device and partition parsing and selection code. This
adds a common function to replace various implementations.
The new function has an enhancement over current versions. If no device
or partition is specified on the command line, the bootdevice env variable
will be used (scsiboot does this).
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Determine which partitions are bootable/active. In the partition listing,
print "Boot" for partitions with the bootable/active flag set.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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All the raw block load commands duplicate the same code. Starting with
the ide version as it has progress updates convert ide, usb, and scsi boot
commands to all use a common version.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Currently the -PC variants of the P1/P2 RDB boards do not print it on boot --
e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect,
this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC,
resulting in a board that does not boot.
P1024RDB and P1025RDB are not included, as these boards apparently do not
have -PC as part of their name, even though they are supported by p1_p2_rdb_pc.
The P2020RDB variant covered by this is apparently P2020RDB-PCA rather
than P2020RDB-PC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:
setenv bootmaster SRIO1
saveenv
The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the "bootmaster" variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to "bootmaster"
based on the using SRIO port.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This makes it easier to include this header from other headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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This function should also be part of the GPIO API, so add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Update Makefile change for LIBS -> LIBS-y change.
Conflicts:
Makefile
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Uma Shankar <uma.shankar@samsung.com>
Signed-off-by: Manjunatha C Achar <a.manjunatha@samsung.com>
Signed-off-by: Iqbal Shareef <iqbal.ams@samsung.com>
Signed-off-by: Hakgoo Lee <goodguy.lee@samsung.com>
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Signed-off-by: Uma Shankar <uma.shankar@samsung.com>
Signed-off-by: Manjunatha C Achar <a.manjunatha@samsung.com>
Signed-off-by: Iqbal Shareef <iqbal.ams@samsung.com>
Signed-off-by: Hakgoo Lee <goodguy.lee@samsung.com>
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This patch fixes the build error for MCF537x. As the NANDFLASH_SIZE is
redefined in boards.cfg, it is needed to rename NANDFLASH_SIZE into
CONFIG_NANDFLASH_SIZE in include/configs/M5373EVB.h.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:
- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
[added include fsl_esdhc header to prevent implicit declarations of
fsl_esdhc_mmc_init() and fdt_fixup_esdhc()]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This is very useful on a modern system.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Change the syntax (user API) for "env default":
-f: override write-once variables
var... : accept individual variable(s)
-a: all (resetting the whole env is NOT the default behavior)
Enable variable checking and make changes effective by
enabling do_apply argument to himport_r().
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
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Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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Change hashtable so that a callback function will decide whether a
variable can be overwritten, and possibly apply the changes.
So add a new field to struct hsearch_data:
o "apply" callback function to check whether a variable can be
overwritten, and possibly immediately apply the changes;
when NULL, no check is performed.
And a new argument to himport_r():
o "do_apply": whether to call the apply callback function
NOTE: This patch does not change the current behavior.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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Add 2 new arguments to himport_r():
o "nvars", "vars": number and list of variables to take into account
(0 means ALL)
NOTE: This patch does not change the current behaviour.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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The logic of checking special parameters (e.g. baudrate, stdin, stdout,
for a valid value and/or whether can be overwritten) and applying the
new value to the running system is now all within a single function
env_check_apply() which can be called whenever changes are made
to the environment, no matter if by set, default or import.
With this patch env_check_apply() is only called by "env set",
retaining previous behavior.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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This board is the only board that still sticks to OneNAND IPL.
Remove this board, since we have SPL around for a while and
OneNAND is well supported in the SPL framework. The board can
be revived if necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tom Rini <trini@ti.com>
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Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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There is no reason to have board configs to select the NFC IP revision. Just let
the driver detect it. BTW, remove broken NFC IP revision configs from board
config files.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <computersforpeace@gmail.com>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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NAND_CMD_ constants for lock/unlock should be in the header
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Missed in previous cleanup.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[scottwood@freescale.com: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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This commit enables multibus handling at Samsung's Trats development board.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Heiko Schocher <hs@denx.de>
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Support for multiple soft I2C buses.
Multibus I2C support is achieved by defining get_multi_{sda|scl}_pin
functions to switch between multiple "soft" I2C buses.
Common definition of I2C_X I2C buses is provided at <i2c.h>.
TEST HW:
Samsung's Exynos4210 evt.0.1 - Trats development board
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Heiko Schocher <hs@denx.de>
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