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* | armv7: make gpmc_cfg constLadislav Michl2016-07-22-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | spl: support loading from UBI volumesLadislav Michl2016-07-22-0/+4
| | | | | | | | | | | | | | | | Add support for loading from UBI volumes on the top of NAND and OneNAND. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-22-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | onenand_spl_simple: Add a simple OneNAND read functionLadislav Michl2016-07-22-0/+1
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* | nand_spl_simple: Add a simple NAND read functionThomas Gleixner2016-07-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | To support UBI in SPL we need a simple NAND read function. Add one to nand_spl_simple and keep it as simple as it goes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | i2c_eeprom: Add reading supportmario.six@gdsys.cc2016-07-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the reading functionality for the generic I2C EEPROM driver, which was just a non-functional stub until now. Since the page size will be of importance for the writing support, we add suitable members to the private data structure to keep track of it. Compatibility strings for a range of at24c* chips are added. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-93/+2
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| * | zynq: defconfig: Remove unnecessary board specific config filesSiva Durga Prasad Paladugu2016-07-22-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary board specifc config files for zynq boards(microzed, picozed, ZC770(all), zed) and point to zynq common config file. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfigSiva Durga Prasad Paladugu2016-07-22-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | Enable config CONFIG_SYS_NO_FLASH through defconfig for all zynq boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | usb: zynq: Define config USB_STORAGE through defconfigSiva Durga Prasad Paladugu2016-07-22-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Define config USB_STORAGE through defconfig for all respective zynq boards Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQSiva Durga Prasad Paladugu2016-07-22-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Enable AHCI on EP platformAlexander Graf2016-07-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The EP platform also has working AHCI emulation, so I see little reason not to implement the plumbing for it that enables us to boot from AHCI. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Remove empty ifdef around cachesMichal Simek2016-07-22-4/+0
| | | | | | | | | | | | | | | | | | Code around was removed because of move to Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-07-21-44/+87
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| * | powerpc/85xx: Increase fdt addressScott Wood2016-07-21-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading the fdt at 0xc00000 fails if the uncompressed kernel image is greater than 12 MiB, which is quite common with modern kernels and multiplatform defconfigs. Move fdtaddr to 0x1e00000 which is just under the ramdiskaddr on most targets. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Paul Gortmaker <paul.gortmaker@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mpc83xx: make it bootable with the latest kernelKevin Hao2016-07-21-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the blow up of the latest kernel size, the default gnuzip size (8M) seems too small. The yocto kernel size I built for mpc8315erdb board is 5294393, and it can't be boot by using the latest u-boot. So expand gnuzip buffer for all the mpc83xx boards to fix this issue. Robert P. J. Day also pointed that the kernel partition on the NAND flash is also too small, fix it at the same time. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mpc83xx: fix the corruption of u-boot when saveenvKevin Hao2016-07-21-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Robert P. J. Day has pointed that the value of SYS_MONITOR_LEN in MPC8315ERDB.h is smaller than the u-boot.bin. This will cause the overlap between the code of u-boot and the environment variable. So when executing saveenv, it will corrupt the code of u-boot and causes the board not boot. Fix this for all the mpc83xx boards by reserving a 512K area. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: MPC8544DS: revert typo in I2C offset valueBenjamin Kamath2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C offset was changed by commit 00f792e0 (added multibus support) from 0x3100 to 0x3000. This typo leads to error when reading SPD from DDR DIMMs. Signed-off-by: Benjamin Kamath <bkamath@spaceflight.com> Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | image: fix IH_ARCH_... values for uImage compatibilityMasahiro Yamada2016-07-21-0/+13
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 555f45d8f916 ("image: Convert the IH_... values to enums") accidentally changed some IH_ARCH_... values. Prior to that commit, there existed a gap between IH_ARCH_M68K and IH_ARCH_MICROBLAZE, like follows. #define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ #define IH_ARCH_M68K 12 /* M68K */ #define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ #define IH_ARCH_NIOS2 15 /* Nios-II */ The enum conversion broke the compatibility with existing uImage files. Reverting 555f45d8f916 will cause build error unfortunately, so here is a more easy fix. I dug the git history and figured out the gap was introduced by commit 1117cbf2adac ("nios: remove nios-32 arch"). So, I revived IH_ARCH_NIOS just for filling the gap. I added comments to each enum block. Once we assign a value to IH_... it is not allowed to change it. Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-14/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * | ARMv8/ls1043ardb: Integrate FSL PPAHou Zhiqiang2016-07-19-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PPA use PSCI to make secondary cores bootup. So when PPA was enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method between PSCI and spin-table. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-14/+0
| | | | | | | | | | | | | | | | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* | | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | | configs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entriesTom Rini2016-07-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code had assumed 4 CPUS before and now we have this configurable. For now, set this to the previous default. Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-0/+11
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| * | | sunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7iChen-Yu Tsai2016-07-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both sun6i and sun7i have 64 KB of secure SRAM. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | ARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled platformsChen-Yu Tsai2016-07-15-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original PSCI implementation assumed CONFIG_ARMV7_PSCI_NR_CPUS=4. Add this to platforms that have not defined it, using CONFIG_MAX_CPUS if it is defined, or the actual number of cores for the given platform. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for sun7iChen-Yu Tsai2016-07-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | sun7i has 2 CPUs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-2/+108
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| * | | dm: core: Add an implementation of regmap_init_mem_platdata()Simon Glass2016-07-14-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of this function which mirrors the functions of the automatic device-tree implementation. This can be used with of-platdata to create regmaps. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Expand platdata for of-platdata devicesSimon Glass2016-07-14-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices which use of-platdata have their own platdata. However, in many cases the driver will have its own auto-alloced platdata, for use with the device tree. The ofdata_to_platdata() method converts the device tree settings to platdata. With of-platdata we would not normally allocate the platdata since it is provided by the U_BOOT_DEVICE() declaration. However this is inconvenient since the of-platdata struct is closely tied to the device tree properties. It is unlikely to exactly match the platdata needed by the driver. In fact a useful approach is to declare platdata in the driver like this: struct r3288_mmc_platdata { struct dtd_rockchip_rk3288_dw_mshc of_platdata; /* the 'normal' fields go here */ }; In this case we have dt_platadata available, but the normal fields are not present, since ofdata_to_platdata() is never called. In fact driver model doesn't allocate any space for the 'normal' fields, since it sees that there is already platform data attached to the device. To make this easier, adjust driver model to allocate the full size of the struct (i.e. platdata_auto_alloc_size from the driver) and copy in the of-platdata. This means that when the driver's bind() method is called, the of-platdata will be present, followed by zero bytes for the empty 'normal field' portion. A new DM_FLAG_OF_PLATDATA flag is available that indicates that the platdata came from of-platdata. When the allocation/copy happens, the DM_FLAG_ALLOC_PDATA flag will be set as well. The dtoc tool is updated to output the platdata_size field, since U-Boot has no other way of knowing the size of the of-platdata struct. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Rename DM_NAME_ALLOCED to DM_FLAG_NAME_ALLOCEDSimon Glass2016-07-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is a flag. Adjust the name to be consistent with the other flags. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: clk: Add support for of-platdataSimon Glass2016-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: Add a header that provides access to the of-platdata structsSimon Glass2016-07-14-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header can be included from anywhere, but will only pull in the of-platdata struct definitions when this feature is enabled (and only in SPL). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: syscon: Add support for of-platdataSimon Glass2016-07-14-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a new function which can cope with obtaining information from of-platdata instead of the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: regmap: Add a dummy implementation for of-platdataSimon Glass2016-07-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a placeholder for now so that this code will compile. It currently does nothing. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Add a test device that uses of-platdataSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start up the test devices. These print out of-platdata contents, providing a check that the of-platdata feature is working correctly. The device-tree changes are made to sandbox.dts rather than test.dts. since the former controls the of-platdata generation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Add a new sandbox_spl boardSimon Glass2016-07-14-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to build SPL for sandbox. It provides additional build coverage and allows SPL features to be tested in sandbox. However it does not need worthwhile to always create an SPL build. It nearly doubles the build time and the feature is (so far) seldom used. So for now, create a separate build target for sandbox SPL. This allows experimentation with this new feature without impacting existing workflows. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Don't use IDE and iotrace in SPLSimon Glass2016-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | These functions are not supported in SPL, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Allow chaining from SPL to U-Boot properSimon Glass2016-07-14-0/+25
| |/ / | | | | | | | | | | | | | | | | | | | | | SPL is expected to load and run U-Boot. This needs to work with sandbox also. Provide a function to locate the U-Boot image, and another to start it. This allows SPL to function on sandbox as it does on other archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Add warn_non_spl() to show a message in U-Boot properSimon Glass2016-07-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPL tends to be more space-constrained that U-Boot proper. Some error messages are best suppressed in SPL. Add a macros to make this easy. warn_non_spl() does nothing when built in SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Add comments for debug() and pr_fmtSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | | | | | Add a note to each of these so it is more obvious how they work. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | stm32: Add SDRAM support for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SDRAM support for stm32f746 discovery board. This patch depends on previous patch. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | | stm32: clk: Add 200MHz clock configuration for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 200MHz clock configuration for stm32f746 discovery board. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | | dragonboard410c: adding missing default addr for script and pxe bootRicardo Salveti de Araujo2016-07-14-0/+2
| | | | | | | | | | | | | | | Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net>
* | | dragonboard410c: prefer sdcard boot over emmcRicardo Salveti de Araujo2016-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the external devices the preferred ones when booting the system (usb is already the first option). This allows users to easily boot custom distributions without requiring them to reflash/customize u-boot. Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Andreas Färber <afaerber@suse.de> Acked-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* | | image: Add functions to obtain category informationSimon Glass2016-07-14-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic functions which can look up information about a category: - the number of items in the category - the category description - an item long time - an item short time Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-19 10:24:40 +0000