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* sandbox: add ADC unit testsPrzemyslaw Marczak2015-11-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This commit adds unit tests for ADC uclass's methods using sandbox ADC. Testing proper ADC binding: - dm_test_adc_bind() - device binding - dm_test_adc_wrong_channel_selection() - checking wrong channel selection Testing ADC supply operations: - dm_test_adc_supply(): - Vdd/Vss values validating - Vdd regulator updated value validating - Vdd regulator's auto enable state validating Testing ADC operations results: - dm_test_adc_single_channel_conversion() - single channel start/data - dm_test_adc_single_channel_shot() - single channel shot - dm_test_adc_multi_channel_conversion() - multi channel start/data - dm_test_adc_multi_channel_shot() - multi channel single shot Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos5-dt-types: add board detection for Odroid XU3/XU3L/XU4.Przemyslaw Marczak2015-11-02-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds additional file with implementation of board detection code for Odroid-XU3/XU4. The detection depends on compatible found in fdt: - "samsung,exynos5" - uses Exynos5 generic code - "samsung,odroidxu3" - try detect XU3 revision There are few revisions of Odroid XU3/XU4, each can be detected by checking the value of channel 9 of built-in ADC: Rev ADC Board 0.1 0 XU3 0.1 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT 0.3 1280 XU4 0.1 The detection code depends on the ADC+10% value. Implementation of functions: - set_board_type() - read ADC and set type - get_board_rev() - returns board revision: 1..3 - get_board_type() - returns board type string Additional functions with return values of bool: - board_is_generic() - true if found compatible "samsung,exynos5" but not "samsung,odroidxu3" - board_is_odroidxu3() - true if found compatible "samsung,odroidxu3" and one of XU3 revision. - board_is_odroidxu4() - true if found compatible "samsung,odroidxu3" and XU4 revision. After I2C controller init, the get_board_type() can check if the XU3 board is a "Lite" variant, by probing chip 0x40 on I2C0 (INA231 - exists only on non-lite). This is useful for setting fdt file name at misc_init_r(). Enabled configs: - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - CONFIG_ODROID_REV_AIN - CONFIG_REVISION_TAG - CONFIG_BOARD_TYPES Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: adc: add simple ADC uclass implementationPrzemyslaw Marczak2015-11-02-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - new uclass id: UCLASS_ADC - new uclass driver: drivers/adc/adc-uclass.c The new uclass's API allows for ADC operation on: * single-channel with channel selection by a number * multti-channel with channel selection by bit mask ADC uclass's functions: * single-channel: - adc_start_channel() - start channel conversion - adc_channel_data() - get conversion data - adc_channel_single_shot() - start/get conversion data * multi-channel: - adc_start_channels() - start selected channels conversion - adc_channels_data() - get conversion data - adc_channels_single_shot() - start/get conversion data for channels selected by bit mask * general: - adc_stop() - stop the conversion - adc_vdd_value() - positive reference Voltage value with polarity [uV] - adc_vss_value() - negative reference Voltage value with polarity [uV] - adc_data_mask() - conversion data bit mask The device tree can provide below constraints/properties: - vdd-polarity-negative: if true: Vdd = vdd-microvolts * (-1) - vss-polarity-negative: if true: Vss = vss-microvolts * (-1) - vdd-supply: phandle to Vdd regulator's node - vss-supply: phandle to Vss regulator's node And optional, checked only if the above corresponding, doesn't exist: - vdd-microvolts: positive reference Voltage [uV] - vss-microvolts: negative reference Voltage [uV] Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: regulator: add function device_get_supply_regulator()Przemyslaw Marczak2015-11-02-0/+16
| | | | | | | | | | | | Some devices are supplied by configurable regulator's output. But there was no function for getting it. This commit adds function, that allows for getting the supply device by it's phandle. The returned regulator device can be used with regulator uclass's API. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: pmic: add s2mps11 PMIC I/O driverPrzemyslaw Marczak2015-11-02-0/+109
| | | | | | | | | | | | | | | | | | This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs. To enable it, update defconfig with: - CONFIG_PMIC_S2MPS11 and additional, if were not defined: - CONFIG_CMD_PMIC - CONFIG_ERRNO_STR The binding info: doc/device-tree-bindings/pmic/s2mps11.txt Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-69/+1547
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| * ls102xa: Adjust some macros for SD boot on LS1021A QDS boardAlison Wang2015-10-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As more features are added for SD boot on LS1021A QDS board, the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS needs to be adjusted to a suitable value. Starting address of the malloc pool used in SPL needs to be adjusted too, or it will occupy the address u-boot loads. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * configs: ls1021atwr: Enable ID EEPROM for SD bootYao Yuan2015-10-30-2/+0
| | | | | | | | | | | | | | | | I2C1 can work on ls102xa rev2.0 SD boot, so add ID EEPROM for SD boot. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund2015-10-30-0/+2
| | | | | | | | | | | | | | | | | | SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Set fdt_high and initrd_high to the value of 0xffffffffAlison Wang2015-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel fails to access the device tree blob on boot. The reason is that u-boot relocates the device tree blob into high memory when booting the kernel and the kernel is unable to access the blob. To avoid this issue, fdt_high is set to the value of 0xffffffff. The device tree blob will not get relocated and is still in low memory to make it accessible to the kernel. For the same reason, initrd_high is set to the value of 0xffffffff too. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Enable secondary coresHou Zhiqiang2015-10-29-0/+3
| | | | | | | | | | | | | | | | | | | | After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add sd boot supportGong Qianyu2015-10-29-1/+40
| | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-1/+12
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-0/+37
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+73
| | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| * armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: fix MDIO controller base on FMAN2Shaohui Xie2015-10-29-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two FMANs, so we should only define MDIO controller base on FMAN2 when there is FMAN2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: Move some header files to include/Shaohui Xie2015-10-29-0/+896
| | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-2/+36
| | | | | | | | | | | | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * common/board_f.c: change the macro name and remove it for PPC platformsGong Qianyu2015-10-29-40/+18
| | | | | | | | | | | | | | | | | | | | For most PPC platforms, they will call the first get_clocks() in init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is then defined to call the second get_clocks(), which should be redundant for PPC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: ls2085ardb: enable CONFIG_PHY_AQUANTIAShaohui Xie2015-10-29-0/+1
| | | | | | | | | | | | | | To support on board Aquantia's PHY AQR405. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: SEC driver cleanup for 64 bit and endiannessAneesh Bansal2015-10-29-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Pointers in ESBC header made 32 bitAneesh Bansal2015-10-29-7/+7
| | | | | | | | | | | | | | | | | | | | For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: Add QSPI or IFC support in SD bootAlison Wang2015-10-26-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE: modify the address of qe ucodeZhao Qiang2015-10-26-2/+2
| | | | | | | | | | | | | | The address of uboot changed, so change qe ucode Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/fsl-ls: Add CONFIG_OF_STDOUT_VIA_ALIASScott Wood2015-10-26-0/+3
| | | | | | | | | | | | | | | | This will allow OF-based earlycon to be used once the appropriate aliases are added to the device tree and kernel support is fixed. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-10-29-3/+5
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| * | net: mdio: Add mdio_free() and mdio_unregister() APIBin Meng2015-10-29-0/+2
| | | | | | | | | | | | | | | | | | | | | Currently there is no API to uninitialize mdio. Add two APIs for this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Increase the size of the net_boot_file_name bufferJacob Stiffler2015-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The net_boot_file_name buffer is used as storage for the bootfilename command line argument to network boot commands such as tftp and nfs. Increase the size of this buffer to 1024 bytes as the current size of 128 bytes is restrictive for arbitrary paths on the server. Signed-off-by: Jacob Stiffler <j-stiffler@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: change the env name to use constJosh Wu2015-10-28-2/+2
| |/ | | | | | | | | | | | | | | As we don't modify the 'name' parameter, so change it to const. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-10-28-4/+17
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| * | sf: Add FSR support to spi_flash_cmd_wait_readyJagan Teki2015-10-25-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds flag status register reading support to spi_flash_cmd_wait_ready. Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Hou Zhiqiang <B48286@freescale.com> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | sf: Make flash->flags use for generic usageJagan Teki2015-10-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the flash->flags for generic usage, not only for dm-spi-flash, this will be used for future flag additions. [Correct the spi flash flags detect logic] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | zynq-common: Add SPL SPI offset, size configsSiva Durga Prasad Paladugu2015-10-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CONFIG_SYS_SPI_ARGS_OFFS, CONFIG_SYS_SPI_ARGS_SIZE and CONFIG_SYS_SPI_KERNEL_OFFS which will be used in SPL spi mode. These macros defines the device tree offset, size and the kernel image offset in flash respectively. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | zynq-common: Enable ISSI SPI-NOR flash supportJagan Teki2015-10-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch enabled CONFIG_SPI_FLASH_ISSI for qspi on zynq boards. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * | zynq-common: Enable Bank/Extended address register supportJagan Teki2015-10-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled SPI flash Bank/Extended address register support. Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | zynq-common: Enable zynq qspi controller supportJagan Teki2015-10-25-0/+9
| |/ | | | | | | | | | | | | | | | | | | | | This patch adds support for zynq qspi controller driver on zynq-common.h Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2015-10-27-868/+0
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| * | ocotea: DropTom Rini2015-10-27-194/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | taishan: DropTom Rini2015-10-27-193/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ebony: DropTom Rini2015-10-27-174/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | taihu: RemoveTom Rini2015-10-27-307/+0
| |/ | | | | | | | | | | | | | | | | | | This board has not compiled for me for quite some time due to size constraints, remove. Cc: John Otken <jotken@softadvances.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://www.denx.de/git/u-boot-cfi-flashTom Rini2015-10-27-4/+4
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| * | cfi_flash: use specific width types for cwordRyan Harkin2015-10-27-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the cword union to use specific length types that are architecture indepented. This patch also renames the members of the cword union to represent their usage, i.e.: c -> w8 s -> w16 l -> w32 ll -> w64 Where "w" stands for "width" in bits. I discovered this problem when enabling CFI flash on vexpress64. cword.l was an unsigned long int, but it was intended to be 32 bits wide. Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a 64-bit system fails when attempting to use 32-bit wide CFI flash parts. Similar problems also existed with the other cword sizes. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-27-125/+66
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| * | dm: tpm: Remove every compilation switch for TPM driver modelChristophe Ricard2015-10-23-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As every TPM drivers support UCLASS_TPM, we can only rely on DM_TPM functions. This simplify a bit the code. Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Tidy up comments in device.hSimon Glass2015-10-23-3/+16
| | | | | | | | | | | | | | | | | | | | | Correct a few nits found in a recent review. Expand the comments in dev_get_driver_data() to make it clearer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Remove a comment about dropping per_child_auto_alloc_sizeSimon Glass2015-10-23-4/+0
| | | | | | | | | | | | | | | | | | | | | This has proven useful and we no-longer intend to remove it. Drop the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-07 16:14:05 +0000