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* Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2014-06-24-1/+1
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| * include/dm.h: fix inclusion guardJeroen Hofstee2014-06-21-1/+1
| | | | | | | | | | | | cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Simon Glass <sjg@chromium.org>
* | mpc8313: add CONFIG_SYS_GENERIC_BOARD to ids8313 boardHeiko Schocher2014-06-23-1/+2
|/ | | | | | | | | - add CONFIG_SYS_GENERIC_BOARD - remove CONFIG_OF_CONTROL to boot again Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: Tidy up four minor code nitsSimon Glass2014-06-20-6/+28
| | | | | | | | | | | | There is a spelling mistake and two functions are missing comments altogether. Also the flags declaration is correct, but doesn't follow style. Finally, the uclass_get_device() function has some errors in its documentation. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* tegra: Enable driver modelSimon Glass2014-06-20-0/+3
| | | | | | | Enable driver model for Tegra boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* tegra: dts: Bring in GPIO bindings from linuxSimon Glass2014-06-20-0/+107
| | | | | | | These files are taken from Linux 3.14. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* dm: Cast away the const-ness of the global_data pointerSimon Glass2014-06-20-0/+4
| | | | | | | In a very few cases we need to adjust the driver model root device, such as when setting it up at initialisation. Add a macro to make this easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Rename struct device_id to udevice_idSimon Glass2014-06-20-3/+3
| | | | | | | It is best to avoid having any occurence of 'struct device' in driver model, so rename to achieve this. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Support iotrace featureSimon Glass2014-06-20-0/+3
| | | | | | | Support the iotrace feature for sandbox, and enable it, using some dummy I/O access methods. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add an I/O tracing featureSimon Glass2014-06-20-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When debugging drivers it is useful to see what I/O accesses were done and in what order. Even if the individual accesses are of little interest it can be useful to verify that the access pattern is consistent each time an operation is performed. In this case a checksum can be used to characterise the operation of a driver. The checksum can be compared across different runs of the operation to verify that the driver is working properly. In particular, when performing major refactoring of the driver, where the access pattern should not change, the checksum provides assurance that the refactoring work has not broken the driver. Add an I/O tracing feature and associated commands to provide this facility. It works by sneaking into the io.h heder for an architecture and redirecting I/O accesses through its tracing mechanism. For now no commands are provided to examine the trace buffer. The format is fairly simple, so 'md' is a reasonable substitute. Note: The checksum feature is only useful for I/O regions where the contents do not change outside of software control. Where this is not suitable you can fall back to manually comparing the addresses. It might be useful to enhance tracing to only checksum the accesses and not the data read/written. Signed-off-by: Simon Glass <sjg@chromium.org>
* includes: move openssl headers to include/u-bootJeroen Hofstee2014-06-19-3/+3
| | | | | | | | | | | | commit 18b06652cd "tools: include u-boot version of sha256.h" unconditionally forced the sha256.h from u-boot to be used for tools instead of the host version. This is fragile though as it will also include the host version. Therefore move it to include/u-boot to join u-boot/md5.h etc which were renamed for the same reason. cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Enhance fit_check_sign to check all imagesSimon Glass2014-06-19-1/+6
| | | | | | | | | At present this tool only checks the configuration signing. Have it also look at each of the images in the configuration and confirm that they verify. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> (v1)
* Avoid including config.h in command.hSimon Glass2014-06-19-1/+0
| | | | | | This is not necessary and prevents using this header when building tools. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootm: Support android boot on sandboxSimon Glass2014-06-19-0/+1
| | | | | | A small change allows this to operate on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* image: Remove the fit_load_image() property parameterSimon Glass2014-06-19-2/+3
| | | | | | | This can be obtained by looking up the image type, so is redundant. It is better to centralise this lookup to avoid errors. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootm: Split out code from cmd_bootm.cSimon Glass2014-06-19-0/+55
| | | | | | | | | | | | | | | | | This file has code in three different categories: - Command processing - OS-specific boot code - Locating images and setting up to boot Only the first category really belongs in a file called cmd_bootm.c. Leave the command processing code where it is. Split out the OS-specific boot code into bootm_os.c. Split out the other code into bootm.c Header files and extern declarations are tidied but otherwise no code changes are made, to make it easier to review. Signed-off-by: Simon Glass <sjg@chromium.org>
* hash: Use uint8_t in preference to u8Simon Glass2014-06-19-1/+2
| | | | | | This type is more readily available on the host compiler, so use it instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* am335x_evm: Only enable OF_CONTROL/OF_SEPARATE on VBOOT for nowTom Rini2014-06-19-3/+3
| | | | | | | | We don't make use of the device tree otherwise yet (and will need to think how to not break the current multi-board support) and this causes further breakage with additional changes. Signed-off-by: Tom Rini <trini@ti.com>
* fdt_support: delete force argument of fdt_chosen()Masahiro Yamada2014-06-19-1/+1
| | | | | | | | | | | | After all, we have realized "force" argument is completely useless. fdt_chosen() was always called with force = 1. We should always want to do the same thing (set appropriate value to the property) even if the property already exists. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* fdt_support: delete force argument of fdt_initrd()Masahiro Yamada2014-06-19-1/+1
| | | | | | | | | | | | After all, we have realized "force" argument is completely useless. fdt_initrd() was always called with force = 1. We should always want to do the same thing (set appropriate value to the property) even if the property already exists. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* configs: iocon: Enabling CONFIG_CMD_FPGAD againMichal Simek2014-06-18-2/+1
| | | | | | | | | | | | | | | | | | | | | This is a MIME GnuPG-signed message. If you see this text, it means that your E-mail or Usenet software does not support MIME signed messages. The Internet standard for MIME PGP messages, RFC 2015, was published in 1996. To open this message correctly you will need to install E-mail or Usenet software that supports modern Internet standards. Revert changes in iocon.h config file caused by these two commits: "configs: iocom: Fix typo on CMD_FPGA command" (sha1: d0db28f94034ef02c1d6737895766fb3c19de47f) and "fpga: Guard the LOADMK functionality with CMD_FPGA_LOADMK" (sha1: 64e809afeaf1572c3246a5bca198a77d0498fd89) CONFIG_CMD_FPGAD is own command. Reported-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* tps6586x.h: fix inclusion guardJeroen Hofstee2014-06-11-1/+1
| | | | | | cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Simon Glass <sjg@chromium.org>
* Add run_command_repeatable()Thomas Betker2014-06-11-0/+1
| | | | | | | | | | run_command() returns 0 on success and 1 on error. However, there are some invocations which expect 0 or 1 for success (not repeatable or repeatable) and -1 for error; add run_command_repeatable() for this purpose. Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* am33xx/omap: Add a new board to enable verified bootSimon Glass2014-06-11-0/+4
| | | | | | Enable verified boot functionality for a new am335x_boneblack_vboot target. Signed-off-by: Simon Glass <sjg@chromium.org>
* am33xx/omap: Enable FIT supportSimon Glass2014-06-11-0/+5
| | | | | | Enable booting a FIT containing a kernel/device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* am33xx/omap: Enable CONFIG_OF_CONTROLSimon Glass2014-06-11-0/+6
| | | | | | | Add support for device tree control and add device tree files for the beaglebone black initially. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: ti: Increase malloc size to 16MB for armv7 boardsSimon Glass2014-06-11-1/+1
| | | | | | | | | The current size of 1MB is not enough use to use DFU. Increase it for ARMv7 boards, all of which should have 32MB or more SDRAM. With this change it is possible to do 'dfu mmc 0' on a Beaglebone Black. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Update functions which write to an FDT to return -ENOSPCSimon Glass2014-06-11-1/+2
| | | | | | | | | | When writing values into an FDT it is possible that there will be insufficient space. If the caller gets a useful error then it can potentially deal with the situation. Adjust these functions to return -ENOSPC when the FDT is full. Signed-off-by: Simon Glass <sjg@chromium.org>
* hash: Export the function to show a hashSimon Glass2014-06-11-0/+14
| | | | | | This function is useful for displaying a hash value, so export it. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-06-10-3/+0
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| * usb: hub: remove CONFIG_USB_HUB_MIN_POWER_ON_DELAYStephen Warren2014-06-01-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we wait the correct specification-mandated time at the end of usb_hub_power_on(), I suspect that CONFIG_USB_HUB_MIN_POWER_ON_DELAY has no purpose. For cm_t35.h, we already wait longer than the original MIN_POWER_ON_DELAY, so this change is safe. For gw_ventana.h, we will wait as long as the original MIN_POWER_ON_DELAY iff pgood_delay was at least 200ms. I'm not sure if this is the case or not, hence I've CC'd relevant people to test this change. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-06-08-77/+393
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| * \ Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-08-17/+170
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| | * | arm:am43xx: Add TPS65218 support to scale voltages upTom Rini2014-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: Tom Rini <trini@ti.com>
| | * | power: Add support for the TPS65218 PMICTom Rini2014-06-06-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini <trini@ti.com>
| | * | board/BuR/common: Add CONFIG_CMD_I2CHannes Petermaier2014-06-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in almost all cases we need the i2c commands within the u-boot shell. So we enable them within the common section. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARDHannes Petermaier2014-06-06-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGSLokesh Vutla2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | loadbootenv expects devtype variable to be set. This is missing in mmcboot command. With this the following error comes: U-Boot# run mmcboot mmc0 is current device SD/MMC found on device 0 ** Bad device usb 0 ** ** Bad device usb 0 ** Fixing this by setting devtype as mmc. Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | tam3517: fix NAND detectionJeroen Hofstee2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND to be set to access flash. Add CONFIG_NAND for tam3517 derived boards to prevent the following error: "nand: error: Unable to find NAND settings in GPMC Configuration - quitting" cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| | * | keystone: k2hk: enable support of nand ecclayout commandWingMan Kwok2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support of nand ecclayout command. Acked-By: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone: init: enable UART1 to be able use it from kernelMurali Karicheri2014-06-06-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | arm:am33xx: Rework s_init and add board_early_init_fTom Rini2014-06-06-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini <trini@ti.com>
| | * | am43xx_evm: Add qspiboot targetSourav Poddar2014-06-06-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * | mtd: nand: omap: add support for BCH16_ECC - NAND driver updatespekon gupta2014-06-06-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap_gpmc: use macro for register definitionspekon gupta2014-06-06-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and ↵pekon gupta2014-06-06-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device ↵pekon gupta2014-06-06-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: fix GET/SET_FEATURES address on 16-bit devicesDavid Mosberger2014-06-06-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." So porting following commit from linux kernel commit e34fcb07a6d57411de6e15a47724fbe92c5caa42 Author: David Mosberger <davidm@egauge.net> (preserving authorship) mtd: nand: fix GET/SET_FEATURES address on 16-bit devices Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: force NAND_CMD_READID onto 8-bit busBrian Norris2014-06-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap_elm: use macros for register definitionspekon gupta2014-06-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros for following parameters of ELM Hardware engine - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
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