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* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2012-09-25-107/+105
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| * powerpc/p1_p2_rdb_pc: print -PC suffix in board nameScott Wood2012-08-23-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the -PC variants of the P1/P2 RDB boards do not print it on boot -- e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect, this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC, resulting in a board that does not boot. P1024RDB and P1025RDB are not included, as these boards apparently do not have -PC as part of their name, even though they are supported by p1_p2_rdb_pc. The P2020RDB variant covered by this is apparently P2020RDB-PCA rather than P2020RDB-PC. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add fine timing support for DDR3York Sun2012-08-23-1/+6
| | | | | | | | | | | | | | | | When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-2/+3
| | | | | | | | | | | | | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-53/+1
| | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * fm-eth: add function fm_info_get_phy_address()Timur Tabi2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | Function fm_info_get_phy_address() returns the PHY address for a given Fman port. This is handy when the MDIO code needs to fixup the Ethernet nodes in the device tree to point to PHY nodes for a specific PHY address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+1
| | | | | | | | | | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/CoreNet: add tool to support pbl image build.Shaohui Xie2012-08-23-0/+9
| | | | | | | | | | | | | | | | | | | | Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Slave module for boot from PCIELiu Gang2012-08-23-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Master module for boot from PCIELiu Gang2012-08-23-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-26/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2012-09-21-0/+12
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| * | fdt: Add header guard to fdtdec.hSimon Glass2012-09-21-0/+3
| | | | | | | | | | | | | | | | | | | | | This makes it easier to include this header from other headers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | Add gpio_request() to asm-generic headerSimon Glass2012-09-21-0/+9
| | | | | | | | | | | | | | | | | | This function should also be part of the GPIO API, so add it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-248/+394
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| * | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-30/+96
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| | * | mx28evk: extend default environmentOtavio Salvador2012-09-17-8/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The environment has been based on mx53loco and m28evk but keeping the possibility to easy change the default console device as Freescale and mainline kernels differ on the device name. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * | MX35: mx35pdk: add support for MMCStefano Babic2012-09-10-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SD card and change the default environment due to increased u-boot size. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | ima3-mx53:Rename CONFIG_PRIME => CONFIG_ETHPRME, removeAshok Kumar Reddy2012-09-10-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | unused macro CONFIG_DISCOVER_PHY Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx31: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
| | * | mx35: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx25: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
| | * | SCSPS1: Enable cachesMarek Vasut2012-09-04-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable caches, make it faster! Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Detlev Zundel <dzu@denx.de>
| | * | mx28evk: Add USB Ethernet supportFabio Estevam2012-09-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB Ethernet support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de>
| | * | M28: Fix the use of gpmi-nand in mtdpartsMarek Vasut2012-09-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mtd name of the NAND in Linux is "gpmi-nand", not "gpmi-nand.0" as it would be expected, since the controller doesn't support multiple NANDs attached to it as of now. Rectify this flub by adjusting default mtdparts. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | MX28: mx28evk: Enable SPI DMAOtavio Salvador2012-09-04-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-51/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | tegra: put eMMC environment into the boot sectorsStephen Warren2012-09-07-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I set up Tegra's config files to put the environment into eMMC, I assumed that CONFIG_ENV_OFFSET was a linearized address relative to the start of the eMMC device, and spanning HW partitions boot0, boot1, general* and the user area in order. However, it turns out that the offset is actually relative to the beginning of the user area. Hence, the environment block ended up in a different location to expected and documented. Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire eMMC. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | mmc: detect boot sectors using EXT_CSD_BOOT_MULT tooStephen Warren2012-09-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to "general" partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Enable NAND on TECThierry Reding2012-09-07-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: enable NAND on HarmonyStephen Warren2012-09-07-2/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: Enable NAND on SeaboardSimon Glass2012-09-07-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables NAND support for the Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | nand: Try to align the default buffersSimon Glass2012-09-07-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | Merge remote-tracking branch 'u-boot-ti/master' into mAlbert ARIBAUD2012-09-05-0/+83
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| | * | | OMAP3: mt_ventoux: added video supportStefano Babic2012-09-04-0/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | | OMAP3: mt_ventoux: activate GPIO4Stefano Babic2012-09-04-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | | OMAP3: tam3517: add function to read MAC from EEPROMStefano Babic2012-09-04-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The manufacturer delivers the TAM3517 SOM with 4 MAC address. They are stored on the EEPROM of the SOM. The patch adds a function to get their values and set the ethaddr variables. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | Merge remote-tracking branch 'u-boot-atmel/master' into mAlbert ARIBAUD2012-09-04-1/+7
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| | * | | Fixes the crippled console output on PortuxG20.Markus Hubig2012-09-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use the serial interface on the PortuxG20 we need to enable the level converter first by setting the PC9 pin to high. The level converter needs some time to settle so we have to use the mdelay() function to wait for some time. Unfortunately we have no timers available at board_early_init_f() so we enable the serial output early within board_postclk_init(). Now the U-Boot output looks fine: | U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32) | | CPU: AT91SAM9G20 | Crystal frequency: 18.432 MHz | CPU clock : 396.288 MHz | Master clock : 132.096 MHz | DRAM: 64 MiB | WARNING: Caches not enabled | NAND: 128 MiB | In: serial | Out: serial | Err: serial | Net: macb0 | Hit any key to stop autoboot: 0 Signed-off-by: Markus Hubig <mhubig@imko.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | atmel: eb_cpux9k2: add ram target configurationJens Scharsig2012-09-04-1/+6
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | * add ram target for EB+CPUx9k2 board (eb_cpux9k2_ram_config) Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | integrator: break out common configLinus Walleij2012-09-04-156/+111
| |/ / | | | | | | | | | | | | | | | | | | | | | The configuration that is common for all Integrator boards may just as well be stored in a common include file as per pattern from other boards. This eases maintenance quite a bit. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | arm/km: remove unused codeHolger Brunck2012-09-03-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reasons we had an own implementaion of dram_init and dram_init_banksize. This is not needed anymore, use the standard kirkwood functions instead. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
| * | arm/km: fix frequency of the SPI NOR FlashValentin Longchamp2012-09-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to our last HW measures, this could be raised while still compatible with the potential delays on the lines. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
| * | km/arm: set SPI NOR Flash default parametersValentin Longchamp2012-09-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These parameters are used by the the sf probe command that are used by our update script and they therefore need to be set for all of our boards. The timing is the same as for the ENV SPI NOR Flash (since it's the same physical device) and takes the boco2 delay on the bus into account. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
| * | edminiv2: orion5x: fix GPIO inits and valuesAlbert ARIBAUD2012-09-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Orion5x did not actually write GPIO output values or input polarities, and ED Mini V2 had bad or missing values for GPIO settings. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* | | Merge branch 'ext4'Tom Rini2012-09-20-81/+343
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Makefile change for LIBS -> LIBS-y change. Conflicts: Makefile Signed-off-by: Tom Rini <trini@ti.com>
| * | | ext4fs write supportUma Shankar2012-08-09-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Uma Shankar <uma.shankar@samsung.com> Signed-off-by: Manjunatha C Achar <a.manjunatha@samsung.com> Signed-off-by: Iqbal Shareef <iqbal.ams@samsung.com> Signed-off-by: Hakgoo Lee <goodguy.lee@samsung.com>
| * | | ext4fs ls load supportUma Shankar2012-08-09-81/+329
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Uma Shankar <uma.shankar@samsung.com> Signed-off-by: Manjunatha C Achar <a.manjunatha@samsung.com> Signed-off-by: Iqbal Shareef <iqbal.ams@samsung.com> Signed-off-by: Hakgoo Lee <goodguy.lee@samsung.com>
generated by cgit v1.1 at 2024-12-13 08:50:23 +0000