| Commit message (Collapse) | Author | Age | Lines |
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add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:
DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:
SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
Signed-off-by Tony Li <tony.li@freescale.com>
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this enables libfdt code by default for the
freescale mpc8313erdb, mpc832xemds, mpc8349emds,
mpc8349itx and gp boards.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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also adds common prototypes to include/common.h.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.
this consequently eliminates CONFIG_ADD_RAM_INFO.
Thanks to Stefan for the hint.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?
uec_init() did not follow the spec for eth_init(), and returned
0 on success. Switch it to return the link like tsec_init()
(and 0 on error)
The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568
CONFIG_QE was off
CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0"
Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The tsec_info structure and array has a "flags" field for each
ethernet controller. This field is the only reason there are
settings. Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Remove unused CFG_NAND_LEGACY define
These boards to not have NAND.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Migrate esd 405EP boards to new NAND subsystem
-cleanup
-use correct io accessors (in/out_be32())
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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since nand_init() is expected to be called by other parts of u-boot, there
should be a prototype for it in nand.h
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Remove a leftover in net/tftp.c while we're at it.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: John Otken <john@softadvances.com>
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This patch was originall provided by David Mitchell <dmitchell@amcc.com>
and fixes a bug in the PLL clock calculation.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)
Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)
Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map
Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
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Change Lime SDRAM initialization to now support 100MHz and
133MHz (if enabled). Also the framebuffer is initialized to
display a blue rectangle with a white border.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
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The used Intel NOR FLASH chips have internally two dies, and are now
treated as two seperate chips.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds ECC Post test for the Lwmon5 board based
on PPC440EPx to U-Boot.
Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Add unlock=yes environment variable to default variables to unlock
the CFI flash by default.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Merge to two at45.c files into a common file, split to at45.c and spi.c
Fix spelling error in DM9161 PHY Support.
Initialize at91rm9200 board (and set LED).
Add PIO control for at91rm9200dk LEDs and Mux.
Change dataflash partition boundaries to be compatible with Linux 2.6.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
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The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.
Signed-off-by Randy Vinson <rvinson@mvista.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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