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* 85xx: Add a 36-bit physical configuration for MPC8572DSKumar Gala2009-01-23-1/+46
| | | | | | | We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Handle eLBC difference w/36-bit physicalKumar Gala2009-01-23-1/+9
| | | | | | | | | | | | The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use BR_ADDR macro for NAND chipselectsKumar Gala2009-01-23-8/+8
| | | | | | | | | Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-1/+5
| | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-0/+4
| | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-0/+3
| | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala2009-01-23-6/+28
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala2009-01-23-26/+56
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boardsKumar Gala2009-01-23-0/+1
| | | | | | | | Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-28/+28
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-52/+52
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate FLASH BASE virtual from physical addressKumar Gala2009-01-23-8/+10
| | | | | | | | | | Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate PIXIS virtual from physical addressKumar Gala2009-01-23-2/+4
| | | | | | | | | | Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2009-01-23-101/+54
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| * NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-74/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: move board_nand_init to nand.hMike Frysinger2009-01-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | Rather than putting the function prototype for board_nand_init() in the one place where it gets called, put it into nand.h so that every place that also defines it gets the prototype. Otherwise, errors can go silently unnoticed such as using the wrong return value (void rather than int) when defining the function. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * OneNAND: Additional sync with 2.6.27Stefan Roese2009-01-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | - Add subpage write support - Add onenand_oob_64/32 ecclayout This has been missing and without it UBI has some incompatibilies issues with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is placed differently (2048 instead of 512) without this fix. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mpc83xx: enable eLBC NAND support for MPC8315ERDB boardDave Liu2009-01-23-5/+7
| | | | | | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
| * Sync with 2.6.27Kyungmin Park2009-01-23-23/+36
| | | | | | | | | | | | Sync with OneNAND kernel codes Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-01-23-50/+71
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| * microblaze: Add cache flushMichal Simek2009-01-23-1/+18
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| * microblaze: Change microblaze-generic config fileMichal Simek2009-01-23-47/+52
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Rename ml401 to microblaze-genericMichal Simek2009-01-23-2/+1
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'fixes'Haavard Skinnemoen2009-01-22-7/+2
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| * avr32: Remove second definition of virt_to_phys()Haavard Skinnemoen2008-12-17-7/+2
| | | | | | | | | | | | | | | | | | | | The second definition introduced by 65e43a1063 conflicts with the existing one. Also, convert the existing definition to use phys_addr_t. The volatile qualifier is still needed due to brain damage elsewhere. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-01-16-0/+52
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| * | sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD2009-01-16-0/+52
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boardsMatthias Fuchs2009-01-14-0/+5
|/ / | | | | | | | | | | | | | | This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-14-0/+1
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| * | Some changes of TLB entry setting for MPC8572DSHaiying Wang2009-01-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | | mpc8610hpcd: Fix PCI mapping conceptsBecky Bruce2009-01-13-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* | | sbc8641d: Fix PCI mapping conceptsBecky Bruce2009-01-13-14/+18
|/ / | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* | at91rm9200: move define from lowlevel_init to headerJean-Christophe PLAGNIOL-VILLARD2009-01-06-0/+27
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | m501sk: move to the common memory setupJean-Christophe PLAGNIOL-VILLARD2009-01-06-0/+33
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD2009-01-06-92/+92
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-12-30-17/+1202
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| * | XPedite5200 board support cleanupPeter Tyser2008-12-29-0/+546
| | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * | sbc8548: use proper PHY addressPaul Gortmaker2008-12-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The values given for the PHY address were wrong, so the code read no valid PHY ID, and fell through to the generic PHY support, which would work on 1000M but would not auto negotiate down to 100M or 10M. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * | sbc8548: enable command line editing by default.Paul Gortmaker2008-12-19-0/+1
| | | | | | | | | | | | | | | | | | Lets make things a bit more user friendly. It isn't 1985 anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * | sbc8548: don't enable the 3rd and 4th eTSECPaul Gortmaker2008-12-19-14/+1
| | | | | | | | | | | | | | | | | | | | | These interfaces don't have usable connectors on the board, so don't bother enumerating or configuring them. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * | mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * | ppc: Use addrmap in virt_to_phys and map_physmem.Kumar Gala2008-12-19-0/+12
| | | | | | | | | | | | | | | | | | | | | If we have addr map support enabled use the mapping functions to implement virt_to_phys() and map_physmem(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Add support to populate addr map based on TLB settingsKumar Gala2008-12-19-0/+3
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | XPedite5370 board supportPeter Tyser2008-12-19-0/+589
| | | | | | | | | | | | | | | | | | | | | | | | Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | Add support for PCA953x I2C gpio devicesPeter Tyser2008-12-19-0/+39
| |/ | | | | | | | | | | | | | | | | | | | | Initial support for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc). The CONFIG_PCA953X define enables support for the devices while the CONFIG_CMD_PCA953X define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO define enables an 'info' sub-command which provides summary information for the given pca953x device. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2008-12-30-1/+1
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| * | MIPS: qemu_mips: move env storage just after u-bootJean-Christophe PLAGNIOL-VILLARD2008-12-17-1/+1
| |/ | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enableJean-Christophe PLAGNIOL-VILLARD2008-12-20-0/+2
|/ | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Remy Böhmer <linux@bohmer.net>
* include/configs/at91cap9adk.h: fix typo.Wolfgang Denk2008-12-16-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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