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* mmc: add generic mmc spi driverThomas Chou2011-04-13-0/+5
| | | | | | | | | | | | | This patch supports mmc/sd card with spi interface. It is based on the generic mmc framework. It works with SDHC and supports multi blocks read/write. The crc checksum on data packet is enabled with the def, There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Andy Fleming <afleming@freescale.com>
* ftwdt010_wdt: move header to include/faraday and enhanceMacpaul Lin2011-04-12-0/+106
| | | | | | | | | | | | | 1. Move header to include/faraday 2. Fix include path in ftwdt010_wdt.c 3. Fix function prototype and declaration to - ftwdt010_wdt_settimeout - ftwdt010_wdt_reset - ftwdt010_wdt_disable 4. Add "#if definde (CONFIG_HW_WATCHDOG)" let user have flexibilty to choose which better to his product. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* Make STANDALONE_LOAD_ADDR configurable per boardWolfgang Denk2011-04-12-0/+2
| | | | | | | | | | | | | Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR and allow that the architecture-specific default value gets overwritten by defining the value in the board header file. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Fix min/max macros in include/common.hAaron Williams2011-04-12-2/+4
| | | | | | | | | | There is a bug in the min and max macros in common.h which occurs if Y is a larger type than X. For example, if Y is a 64-bit value and X is a 32-bit value then Y will be truncated to 32-bits. This fix matches what is done in the Linux kernel but without the additional type checking present in the kernel version. Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
* mp2usb: remove board supportEric BĂ©nard2011-04-11-242/+0
| | | | | | | this board was cancelled long time ago so remove it as it won't be maintained anymore Signed-off-by: Eric Bénard <eric@eukrea.com>
* ppc, mgcoge: add DIP switch detectionAndreas Huber2011-04-11-0/+5
| | | | | | | | | This reads the DIP switch on mgcoge. The DIP switch is connected to the BFTICU (0x40000089) FPGA. If the DIP switch is set the environment variable 'actual_bank' is set to 0 and starts the SW in bank0. Signed-off-by: Andreas Huber <andreas.huber@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* Net: Add Intel E1000 82574L PCIe card supportRoy Zang2011-04-11-0/+1
| | | | | | | | | Add Intel E1000 82574L PCIe card support. Test on MPC8544DS and MPC8572 board. Add the missing contact information for future support. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-10-62/+94
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| * fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-10-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie2011-04-10-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update default hwconfig on P1022DSJiang Yutang2011-04-10-0/+1
| | | | | | | | | | | | | | | | Set default configuration to have SDHC controller enabled, AUDIO enabled(codec clock sources is 12MHz) and disable TDM. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable support for ATI graphics cards on P1022DSJiang Yutang2011-04-10-0/+16
| | | | | | | | | | | | | | Make the support for ATI graphics cards mutually exclusive with DIU. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boardsKumar Gala2011-04-09-23/+0
| | | | | | | | | | | | | | | | We don't really ever use Video cards on corenet_ds style boards and its bloating our image which is close the its max size. Drop support and also kill some defines for non-PNP PCI which we never use. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: rename NAND prefixes to CONFIG_SYSMatthew McClintock2011-04-08-37/+37
| | | | | | | | | | | | | | | | | | | | renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more appropriate CONFIG_SYS prefix as well as be consistent with 83xx. Signed-off-by: Matthew McClintock <msm@freescale.com> cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-04-10-9/+373
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| * | Blackfin: bf548-ezkit: move env sectorMike Frysinger2011-04-08-1/+1
| | | | | | | | | | | | | | | | | | | | | U-Boot itself takes up more than 0x40000 bytes, so we can't use that sector for the environment. Move it down a page. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: adi boards: enable CONFIG_MONITOR_IS_IN_RAMMike Frysinger2011-04-08-0/+2
| | | | | | | | | | | | | | | | | | Our monitor is always in RAM, so enable this define for the CFI layer. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: adi boards: enable ldrinfoMike Frysinger2011-04-08-0/+1
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: adi boards: drop old ELF defineMike Frysinger2011-04-08-1/+0
| | | | | | | | | | | | | | | | | | This define isn't used anywhere anymore, so punt it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bf506f-ezkit: new board portMike Frysinger2011-04-08-0/+102
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bf561-ezkit/ibf-dsp561: invert env offset/addr logicMike Frysinger2011-04-08-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other way around so that we can use CONFIG_ENV_OFFSET during build. It also avoids a little address duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bf537-minotaur/bf537-srv1: undefine nfs when net is disabledMike Frysinger2011-04-08-0/+2
| | | | | | | | | | | | | | | | | | Fixes a build error due to new partial linking logic. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bf525-ucr2: new board portChong Huang2011-04-08-0/+102
| | | | | | | | | | | | | | | | | | Signed-off-by: Chong Huang <chuang@ucrobotics.com> Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: dnp5370: new board portAndreas Schallenberg2011-04-08-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | Info about the hardware can be found here: http://www.dilnetpc.com/dnp0086.htm Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: move CONFIG_BFIN_CPU back to board config.hMike Frysinger2011-04-08-3/+31
| |/ | | | | | | | | | | This is a revert of 821ad16fa9900c as Wolfgang doesn't like the new code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | mtd, cfi: introduce void flash_protect_default(void)Heiko Schocher2011-04-07-0/+1
|/ | | | | | | | collect code which protects default sectors in a function, called flash_protect_default. So boardspecific code can call it too. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-05-53/+236
|\ | | | | | | | | | | | | Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc: clean up DIU macro definitions for Freescale reference boardsTimur Tabi2011-04-04-16/+9
| | | | | | | | | | | | | | | | | | | | | | | | Clean up the macro defintions used to enable DIU (video) support on the MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS, which is newer. Add software cursor support to all three boards. Also document the CONFIG_FSL_DIU_FB in the README. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable eSDHC boot support on P2020 DSJerry Huang2011-04-04-0/+25
| | | | | | | | | | | | | | | | | | | | | | We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statementsKyle Moffett2011-04-04-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add 36-bit address map support to P1022DSJiang Yutang2011-04-04-1/+45
| | | | | | | | | | Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DSZhao Chenhui2011-04-04-0/+14
| | | | | | | | | | | | | | | | MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage device support using PCI EHCI module. Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Disable ECC in considering performance on MPC8572DSZhao Chenhui2011-04-04-1/+1
| | | | | | | | | | Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DSZhao Chenhui2011-04-04-1/+1
| | | | | | | | | | Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDBPoonam Aggrwal2011-04-04-3/+64
| | | | | | | | | | | | | | | | Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Read board switch settings on p1_p2_rdbPriyanka Jain2011-04-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdbPriyanka Jain2011-04-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDBPoonam Aggrwal2011-04-04-2/+3
| | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Refactor Qman/Portal support to be shared between SoCsHaiying Wang2011-04-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-0/+4
| | | | | | | | | | | | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Remove config.mk for nand linker scriptKumar Gala2011-04-04-0/+4
| | | | | | | | | | | | | | Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update P2020DS default env settingsLi Yang2011-04-04-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Read MAC address from EEPROM. Add hwconfig settings. Modified the default othbootargs to include the cache-sram-size parameter. This parameter is needed as the L2 as SRAM is ON by default in the P2020RDB kernel and used by the Gianfar driver. Also cleanup some of the boot commands. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add eSDHC support on P2020DSJerry Huang2011-04-04-1/+24
| | | | | | | | | | | | | | | | | | | | | | We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | MIPS: Purple: Remove Purple supportDaniel Schwierzeck2011-04-02-173/+0
|/ | | | | | | | The Purple SoC and eval board are not actively maintained since years. This patch removes the support completely as aggreed with Wolfgang Denk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* NAND: add support for reading ONFI page tableFlorian Fainelli2011-04-01-0/+69
| | | | | | | | | | | | This patch adds support for reading an ONFI page parameter from a NAND device supporting it. If this is the case, struct nand_chip onfi_version member contains the supported ONFI version, 0 otherwise. This allows NAND drivers past nand_scan_ident to set the best timings for the NAND chip. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-0/+1
| | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang2011-03-28-0/+1
| | | | | | | | | | Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-1/+46
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| * arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h updateTom Warren2011-03-27-1/+1
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-19 15:20:47 +0000