summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeLines
* powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-19-0/+28
| | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-17-1756/+245
|\
| * powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)Kumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | | | | | Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boardsKumar Gala2011-01-14-11/+24
| | | | | | | | | | | | | | CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-14-0/+1
| | | | | | | | | | | | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-1/+3
| | | | | | | | | | | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add SRIO support to P2020DSLi Yang2011-01-14-1/+23
| | | | | | | | | | | | | | | | The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Convert SBC8641 to use common SRIO init codeKumar Gala2011-01-14-6/+9
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Convert MPC8641HPCN to use common SRIO init codeKumar Gala2011-01-14-17/+13
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8569MDS to use common SRIO init codeKumar Gala2011-01-14-4/+8
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8568MDS to use common SRIO init codeKumar Gala2011-01-14-4/+8
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8548CDS to use common SRIO init codeKumar Gala2011-01-14-7/+8
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-1/+3
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+2
| | | | | | | | | | | | | | | | Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-1/+2
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-1/+2
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+3
| | | | | | | | | | | | | | Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+3
| | | | | | | | | | | | | | | | | | Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-0/+3
| | | | | | | | | | | | | | | | | | Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixupKumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_INBecky Bruce2011-01-14-9/+5
| | | | | | | | | | | | | | | | | | This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Fix esdhc disabled problem on some platformsChenhui Zhao2011-01-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak functionKumar Gala2011-01-14-3/+0
| | | | | | | | | | | | Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for booting from NAND on MPC8572DSKumar Gala2011-01-14-15/+100
| | | | | | | | | | | | | | | | Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * MPC8568/MPC8569: Remove CONFIG_DDR_DLL defineBecky Bruce2011-01-14-2/+0
| | | | | | | | | | | | | | | | Neither of these parts should have the erratum this is meant to work around. Delete it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definitionBecky Bruce2011-01-14-6/+0
| | | | | | | | | | | | | | This isn't used - delete it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Remove support for PM854/PM856 boardsKumar Gala2011-01-14-855/+0
| | | | | | | | | | | | | | | | The PM854/PM856 boards are no longer maintained and thus we are removing support for them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/85xx: Removed support for MPC8540EVAL boardKumar Gala2011-01-14-362/+0
| | | | | | | | | | | | | | The MPC8540EVAL board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Removed support for ATUM8548 boardKumar Gala2011-01-14-443/+0
| | | | | | | | | | | | | | The ATUM8548 board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()Lei Wen2011-01-12-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sync with David's patch on Linux for handling nand_scan_ident. commit 5e81e88a4c140586d9212999cea683bcd66a15c6 Author: David Woodhouse <David.Woodhouse@intel.com> Date: Fri Feb 26 18:32:56 2010 +0000 mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident() Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
* | NAND: add the ability to directly write yaffs imageLei Wen2011-01-12-1/+1
|/ | | | | | | This patch add addition suffix to nand write to give the uboot the power to directly burn the yaffs image to nand. Signed-off-by: Lei Wen <leiwen@marvell.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-01-12-0/+130
|\
| * sh: Add support T-SH7706LSR boardNobuhiro Iwamatsu2011-01-06-3/+16
| | | | | | | | | | | | | | | | | | | | This patch supports T-SH7706LSR board. This is constitution almost same as shmin (T-SH7706LAN). Therefore, most functions work by a change of the setting of config. http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706LSR.htm Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: r2dplus: Add support zimagebootNobuhiro Iwamatsu2011-01-11-0/+1
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: sh7785lcr: Add support zimagebootNobuhiro Iwamatsu2011-01-11-0/+1
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add support shmin boardNobuhiro Iwamatsu2011-01-11-0/+115
| | | | | | | | | | | | | | | | | | | | | | This adds support for the SHMIN SH7706 board(T-SH7706LAN). The CPU of this board is SH7706. There are SDRAM of 32M byte, Flash memory of 512K byte, Serial, 10Base Ether and MMC. http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706.htm Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2011-01-12-17/+0
|\ \
| * | ppc4xx: Remove PCI support from lwmon5Stefan Roese2011-01-10-17/+0
| | | | | | | | | | | | | | | | | | | | | PCI is not used at all on lwmon5. So lets remove it. It saves space and reduces boot time a bit (approx. 50ms). Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2011-01-12-4/+4
|\ \ \ | |_|/ |/| |
| * | microblaze: Fix bd_info pointerMichal Simek2011-01-10-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value" (sha1: 25ddd1fb0a2281b182529afbc8fda5de2dc16d96) introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t (currently 0x40). Microblaze configs used 0x40(128) because this place also contained board info structure which lies on the top of ram. U-Boot is placed to the top of the ram (for example 0xd7ffffff) and bd structure was moved out of ram. This patch is fixing this scheme with GENERATED_BD_INFO_SIZE which swap global data and board info structures. For example: Current: gd 0xd7ffffc0, bd 0xd8000000 Fixed: gd 0xd7ffffc0, bd 0xd7ffff90 Signed-off-by: Michal Simek <monstr@monstr.eu>
* | ftgmac100: support of gigabit eth ftgmac100Macpaul Lin2011-01-09-0/+1
|/ | | | | | | Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-83/+8
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2024-12-21 06:50:52 +0000