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* tools: mkimage: Fixed build warningsPrafulla Wadaskar2009-09-10-3/+34
| | | | | | | | uninitialized retval variable warning fixed crc32 APIs moved to crc.h (newly added) and build warnings fixed Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boardsMatthias Fuchs2009-09-10-0/+12
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* amcc-common.h: Use filenames from environment variables for update procedure.Detlev Zundel2009-09-10-3/+5
| | | | | | | | | | Using a separate "u-boot" environment variable allows to easily specify different filenames for the update procedure. This is also in line with many other board configurations defining an "update" script. Signed-off-by: Detlev Zundel <dzu@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-0/+2
| | | | | | | | | | | Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-0/+5
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add a simple function to search the TLBKumar Gala2009-09-08-2/+5
| | | | | | | | | | | Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for setting IVORs to fixed offset defaultsKumar Gala2009-09-08-0/+12
| | | | | | | | | | | | In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-2/+1
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2009-09-07-0/+1
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| * Reset i2c slave devices during init on mpc5xxx cpusEric Millbrandt2009-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | Reset any i2c devices that may have been interrupted during a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). There is no direct access to the i2c pins so instead create start commands through the i2c interface. Send a start command then delay for the SDA Hold time, repeat this by disabling/enabling the bus a total of 9 times. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-09-07-30/+1121
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| * ARM: DaVinci: Adding Support for DaVinci DM365 EVMSandeep Paulraj2009-09-05-0/+182
| | | | | | | | | | | | | | This patch adds support for the DM365 EVM. It has been tested on a DM365 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * Add support for the DevKit8000 boardFrederik Kriewitz2009-09-05-0/+307
| | | | | | | | | | | | This patch adds support for the DevKit8000 board. Signed-off-by: Frederik Kriewitz <frederik@kriewitz.eu>
| * Support for the Calao TNY-A9260/TNY-A9G20 boardsAlbin Tonnerre2009-09-01-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | The Calao TNY-A9260 and TNY-9G20 are boards manufactured and sold by Calao Systems <http://www.calao-systems.com>. Their components are very similar to the AT91SAM9260EK board, so their configuration is based on the configuration of this board. There are however some differences: different clocks, no LCD, no ethernet. They also can use SPI EEPROM to store the environment. Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm: Kirkwood: add SYSRSTn Duration Counter SupportPrafulla Wadaskar2009-09-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature can be used to trigger special command "sysrstcmd" using reset key long press event and environment variable "sysrstdelay" is set (useful for reset to factory or manufacturing mode execution) Kirkwood SoC implements a hardware-based SYSRSTn duration counter. When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter value is stored in the SYSRSTn Length Counter Register The counter is based on the 25-MHz reference clock (40ns) It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, it remains at this value until counter reset is triggered by setting bit 31 of KW_REG_SYSRST_CNT Implementation: Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be executed if pre-defined in environment variables. This feature will be disabled if "sysrstdelay" variable is unset. for-ex. setenv sysrst_cmd "echo starting factory reset; nand erase 0xa0000 0x20000; echo finish ed sysrst command;" will erase particular nand sector if triggered by this event Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * Add support for the Calao SBC35-A9G20 boardAlbin Tonnerre2009-09-01-0/+194
| | | | | | | | | | | | | | | | | | | | | | The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems <http://www.calao-systems.com>. It is built around an AT91SAM9G20 ARM SoC running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND flash, two USB host ports, and an USB device port. More informations can be found at <http://www.calao-systems.com/articles.php?lng=en&pg=5936> Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
| * imx27lite: add support for imx27lite board from LogicPDIlya Yanok2009-09-01-0/+264
| | | | | | | | | | | | | | | | | | This patch adds support for i.MX27-LITEKIT development board from LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND flash, FEC ethernet controller integrated into i.MX27. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Wolfgang Denk <wd@denx.de>
| * Remove duplicate set_crSimon Kagstrom2009-09-01-30/+0
| | | | | | | | | | | | | | | | | | | | Remove duplicate set_cr set_cr is defined in both asm-arm/proc-armv/system.h and include/asm-arm/system.h. This patch removes it (and some duplicate defines) from the former. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* | ARM: Update mach-typesWolfgang Denk2009-09-04-12/+2056
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Move uninitialized_var() macro from ubi_uboot.h to compiler.hAnton Vorontsov2009-09-04-3/+4
| | | | | | | | | | | | This is needed so that we could use this macro for non-UBI code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | galaxy5200: Add chip select region for an Epson S1D15313Eric Millbrandt2009-09-04-0/+5
| | | | | | | | Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* | Add PCI support to eNET boardGraeme Russ2009-09-04-7/+7
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structureGraeme Russ2009-09-04-183/+234
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Misc sc520 cdp fixupsGraeme Russ2009-09-04-22/+0
| | | | | | | | | | | | | | Now that the PCI, SATA et al compile problems have been resolved, the cludge that was applied to avoid them can be removed Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Fixup sc520_spunk boardGraeme Russ2009-09-04-0/+2
| | | | | | | | | | | | | | | | Primary intent is to resolve build errors for this board which has been neglected for a very long time. I do not have one of these boards, so I cannot test functionality Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Misc ds1722 fixupsGraeme Russ2009-09-04-0/+32
| | | | | | | | | | | | | | | | This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | i386: Misc PCI fixupsGraeme Russ2009-09-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in commit ff4e66e93c1a, regressed by commit 6d7f610b09f8) Cast PCI_ROM_ADDRESS_MASK to u32 Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO Change call to pci_find_class() to pci_find_devices(). This is based on a patch submitted on 1st March 2007 (Patch that fixes the compilation errors for sc520_cdp board) by mushtaq_k This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be specified in the board config file. Dummy values have been added for the SC520 CDP board to enable compilation, but since I do not have one of these, I do know what the values should be Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Fix environment configuration for eNET boardGraeme Russ2009-09-04-6/+5
| | | | | | | | | | | | | | | | The current configuration of the Environment has the redundant copy of the environment in the Boot Flash - This was never the intent. The Environment should instead be in the first two sectors of the first Strata Flash Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | i386: Add errno.hGraeme Russ2009-09-04-0/+1
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Consolidate arch-specific mem_malloc_init() implementationsPeter Tyser2009-09-04-0/+2
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Consolidate arch-specific sbrk() implementationsPeter Tyser2009-09-04-0/+6
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Blackfin: enable 64bit printf for nandMike Frysinger2009-09-02-0/+3
| | | | | | | | | | | | | | | | Since the NAND code now uses 64bit code, make sure we enable support for ADI Blackfin boards in printf to avoid the warning: nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: use scratch pad for exception stackMike Frysinger2009-09-02-0/+4
| | | | | | | | | | | | | | | | | | If the memory layout pushes the stack out of the default DCPLB coverage, the exception handler may trigger a double fault by trying to push onto the uncovered stack. So handle the exception stack similar to the kernel by using the top of the scratch pad SRAM. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: increase default console sizeMike Frysinger2009-09-02-5/+1
| | | | | | | | | | | | | | The default console size indirectly applies to length of env vars, so a smaller length makes it hard to pass longer command lines to kernels. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: cm-bf537u: new board portHarald Krapfenbauer2009-09-02-0/+150
| | | | | | | | | | | | | | | | The CM-BF537U is similar to the CM-BF537E module, but enough to need its own board port. Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: change global data register from P5 to P3Robin Getz2009-09-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since the Blackfin ABI favors higher scratch registers by default, use the last scratch register (P3) for global data rather than the first (P5). This allows the compiler's register allocator to use higher number scratch P registers, which in turn better matches the Blackfin instruction set, which reduces the size of U-Boot by more than 1024 bytes... Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: enable more network commands for ADI dev boardsRobin Getz2009-09-02-0/+10
| | | | | | | | | | | | | | | | Add dns and ntp to default networking commands, and ask for more dhcp options to better configure the network environment. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf537-stamp: comment CF-Flash Card Support betterMichael Hennerich2009-09-02-5/+24
| | | | | | | | | | Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: use +(filesize) to make sure we are only doing what is necessaryRobin Getz2009-09-02-2/+2
|/ | | | | Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'next' of ../nextWolfgang Denk2009-08-31-134/+1280
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| * 85xx: Added PCIe support for P1 P2 RDBPoonam Aggrwal2009-08-28-0/+6
| | | | | | | | | | | | | | Call fsl_pci_init_port() to initialize all the PCIe ports on the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+26
| | | | | | | | | | | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-2/+6
| | | | | | | | | | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added CONFIG_MAX_CPUS for P1020Poonam Aggrwal2009-08-28-2/+2
| | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-0/+5
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Fix memory test range on MPC8536DSFelix Radensky2009-08-28-2/+2
| | | | | | | | | | | | | | | | | | | | With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END memory test hangs if run without arguments. Set them to sane values, so that all available 512MB of RAM excluding exception vectors at the bottom and u-boot code and stack at the top can be tested. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Removed BEDBUG support on P1_P2_RDBKumar Gala2009-08-28-1/+0
| | | | | | | | | | | | To match all other 85xx platforms we are removing BEDBUG support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add support for P2020RDB boardPoonam Aggrwal2009-08-28-1/+557
| | | | | | | | | | | | | | | | | | | | | | | | | | The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-26 21:08:30 +0000