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* TI DaVinci DM365: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci DM355: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI: OMAP3: Remove SZ_xx referencesSandeep Paulraj2009-10-18-56/+49
| | | | | | | This patch removes dependency on the sizes.h header file and removes all references to SZ_xx. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3: Update Overo and Beagle environmentSteve Sakoman2009-10-18-16/+38
| | | | | | | | Update default environment to support new kernel DSS2 subsystem and simplify rootfs type and location changes. Signed-off-by: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* TI: DaVinci: DM355 Leopard board supportSandeep Paulraj2009-10-18-0/+162
| | | | | | | This patch adds support for the leopard board which is based on the DM355 SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci DM646x: Adding initial support for DM6467 EVMSandeep Paulraj2009-10-18-0/+132
| | | | | | | This patch adds the initial support for DM6467 EVM. Other features like NET and NAND support will be added as follow up patches. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* AT91 CPUAT91 Fix compiler warningEric Benard2009-10-18-2/+2
| | | | | | | | | | This change fixes the compiler warning main.c: In function 'abortboot': main.c:122: warning: too few arguments for format Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* AT91 CPU9260 CPU9G20 Fix compile warningsEric Benard2009-10-18-0/+1
| | | | | | | | | | This change fixes the compiler warning nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Clean-up of s3c24x0 header fileskevin.morfitt@fearnside-systems.co.uk2009-10-13-1121/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the arm920t s3c24x0 header files in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patch 1/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boardskevin.morfitt@fearnside-systems.co.uk2009-10-13-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and s3c2410 cpu's which fixes various problems such as the timeouts in tftp being too short. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. It was originally submitted on 21/06/2009 but didn't get into the 2009.08 release, and Jean-Pierre made one comment on the original patch (see http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two changes to the original patch: - it's been re-based to the current release - I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it directly to the maintainers of all except the sbc2410 which doesn't have an entry in MAINTAINERS. Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain> Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* s5pc1xx: add support SMDKC100 boardMinkyu Kang2009-10-13-0/+242
| | | | | | | Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* s5pc1xx: support serial driverMinkyu Kang2009-10-13-0/+7
| | | | | | | | This patch includes the serial driver for s5pc1xx. s5pc1xx uart driver needs own register setting and clock configuration. So, need to special driver. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* s5pc1xx: support onenand driverMinkyu Kang2009-10-13-0/+136
| | | | | | | This patch includes the onenand driver for s5pc100 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* s5pc1xx: support Samsung s5pc1xx SoCMinkyu Kang2009-10-13-0/+475
| | | | | | | | This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* at91: Update MEESC board supportDaniel Gorsulowski2009-10-13-17/+8
| | | | | | | | | | | This patch implements several updates: -disable CONFIG_ENV_OVERWRITE -add new hardware style variants and set the arch numbers appropriate -pass the serial# and hardware revision to the kernel -removed unused macros from include/configs/meesc.h -fixed multiline comment style Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
* TI: OMAP3: Overo Tobi ethernet supportOlof Johansson2009-10-13-2/+15
| | | | | | | | | | | | | Add setup for ethernet on Tobi, allowing kernel/ramdisk to be loaded over tftp. This also refactors the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
* TI OMAP3 Use arm init sequence to initialize i2cTom Rix2009-10-13-0/+7
| | | | | | | | | | | | | | | | | | | | | | This changes fixes an early i2c error. It appears that I2C is working because once a read or write error is detected, the omap24xx_i2c driver calls i2c_init inside its error handling check. While it is ok to attempt error handling this way, the boards must not depend on this side effect to initialize it's i2c. Instead of explicitly calling i2c_init for every board, use the generic arm initialization in lib_arm/board.c. By defining the config variable CONFIG_HARD_I2C, the omap3 i2c initialization is included in the init_sequence table. Run tested on Beagle. Compile tested on the omap3's Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
* TI: DaVinci: GPIO header file and definitionsSandeep Paulraj2009-10-13-0/+53
| | | | | | | | | | | Some DaVinci SOC's use GPIOs to enable EMAC and DM9000. This patch adds some definitions for GPIO registers and also adds structures for GPIO. A separate header file is being added so that in future we can have a DaVinci GPIO driver similer to OMAP. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* TI: DaVinci DM646x: Update flag used to represent DM646x SOC'sSandeep Paulraj2009-10-13-3/+3
| | | | | | | | | | | In the DaVinci specific code, we use both CONFIG_SOC_DM646X and CONFIG_SOC_DM646x to represent DM646x specific code. This patch changes occurrences of CONFIG_SOC_DM646x to CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use the flag CONFIG_SOC_DM644X. We want some uniformity. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* OMAP3 MMC: Fix warning dereferencing type-punned pointerDirk Behme2009-10-13-0/+7
| | | | | | | | | Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Steve Sakoman <sakoman@gmail.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
* Support for the OpenRD base boardSimon Kagstrom2009-10-13-0/+220
| | | | | | | The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-0/+453
| | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-0/+306
| | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* TI: DaVinci DM365: Minor config cleanupSandeep Paulraj2009-10-13-2/+0
| | | | | | | | | | The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag. This is already included when we include the config_cmd_default.h header file. So this flag is removed. Also another flag to enable NAND functions was being enabled incorrectly. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM355: Config Cleanup and UpdateSandeep Paulraj2009-10-13-9/+12
| | | | | | | | | | | | | | | | | | This patch does the following 1) Enables the NAND driver which is now available. 2) Enables the 'CONFIG_MTD_DEVICE' as without this the compilation will fail 3) We now have a safe place to store environment and defines an offset where this can be stored. This offset value is such that it is after the location where U-Boot is flashed using TI flash utilities. 4) Enables Bootdelay 5) Increases malloc() arena size. Manufacturers are coming out with NAND with large blocks sizes of upto 1 MiB. It has been noticed that as the block size of the NAND used is increased, if this particular value is not increased, the NAND driver will output out of memory errors. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM646x: Initial Support for DM646x SOCSandeep Paulraj2009-10-13-0/+11
| | | | | | | | | DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* TI DaVinci: DM6446: Fix Compilation error in NAND modeSandeep Paulraj2009-10-13-0/+1
| | | | | | | | | | | | The Default mode that is built for the Davinci DVEVM happens to be the NOR mode. When we want to build for the NAND mode, we get a compilation error. This is overcome by defining the CONFIG_MTD_DEVICE flag in the NAND mode. The image built for NAND mode was successfully tested on the DaVinci DM6446 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3 Move cache routine to cache.STom Rix2009-10-13-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* TI DaVinci: Remove references to SZ_xxSandeep Paulraj2009-10-13-19/+13
| | | | | | | | | | This patch removes the asm/sizes.h header file from being included in the DaVinci SOC configs. References to SZ_xx have been replaced by appropriate bit shifted values. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Wolfgang Denk <wd@denx.de>
* Update all board to support new bbmiiphy driver (with multibus support)Luigi 'Comio' Mantellini2009-10-10-0/+74
| | | | | Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an ↵Luigi 'Comio' Mantellini2009-10-10-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arbitrary number of mii buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define at least the following macros: MII_INIT - Generic code to enable the MII bus (optional) MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin (optional) MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill the bb_miiphy_buses[] array with a record for each required bus and declare the bb_miiphy_buses_num variable with the number of mii buses. The record (struct bb_miiphy_bus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-29/+23
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| * ppc: Remove reloc_off field from global_data structurePeter Tyser2009-10-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that proper relocation is supported, the reloc_off field is no longer necessary. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We therefore increment XF_VERSION to 6 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * arm/microblaze/nios/nios2/sh: Remove relocation fixupsPeter Tyser2009-10-03-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These architectures don't need relocation fixups, so reduce their codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS. Also remove the reloc_off field from their global data structures as it is no longer needed. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. We will therefore increment XF_VERSION in the next commit, which also touches this area. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Conditionally perform common relocation fixupsPeter Tyser2009-10-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * p3mx: Remove serial relocation fixupsPeter Tyser2009-10-03-1/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * fpga: Remove relocation fixupsPeter Tyser2009-10-03-17/+1
| | | | | | | | | | | | | | | | PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove board-specific command table relocation fixupsPeter Tyser2009-10-03-1/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | tqm5200: Correct comment and code in post_hotkeys_pressed.Detlev Zundel2009-10-08-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the code and the comment according to the original intent of doing an intensive memory test when PSC6_3 is pulled low on the STK52xx. Notably PORT_CONFIG will be overridden with this correct code now, so beware. The original code only worked by coincidence depending on the PORT_CONFIG setting from the header file. The new code was tested to ensure that the (undocumented) memory test still works on the STK52x. Signed-off-by: Detlev Zundel <dzu@denx.de> CC: Martin Krause <Martin.Krause@tqs.de> Minor white-space cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | mpc512x: fix fixed_sdram() init code.Wolfgang Denk2009-10-08-1/+12
| | | | | | | | | | | | | | | | | | | | Commit 054197ba and later fixes used an array to initialize some of the MDDRC parameters; however, the use of an array turned out to be a bad idea as it was not possible to correlate structure entries to array indices in readable and reliable way. Now we use a struct instead, which makes this self-explanatory. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: respect 80-chars per line in ppc*.h filesNiklaus Giger2009-10-07-870/+1038
| | | | | | | | | | | | | | | | After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Cleanup some HW register namesNiklaus Giger2009-10-07-189/+216
| | | | | | | | | | | | | | | | | | | | Here you find all the changes in the include directory for new register names and adapting other ones to the names used by AMCC in their manuals, e.g. For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008 For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006 Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add PPC405EX(r) Rev D supportStefan Roese2009-10-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com>
* | Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI APIBen Warren2009-10-04-38/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | net: add random_port() prototypeMike Frysinger2009-10-04-0/+3
| | | | | | | | | | | | | | | | | | | | The random_port() is meant to be used by other net code, but without a prototype, we get fun warnings like: dns.c: In function 'DnsSend': dns.c:89: warning: implicit declaration of function 'random_port' Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-10-03-4/+4
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| * | ppc4xx: Add SDRAM detection for PMC440 boardsMatthias Fuchs2009-10-02-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to detect the amount of DDR2 SDRAM on PMC440 modules. Detection is done by probing through a list of available and supported hardware configurations from 1GByte down to 256MB. The static TLB entry is replaced by dynamically created entries. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Merge PPC4xx DDR and DDR2 ECC handlingStefan Roese2009-10-02-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
| * | ppc4xx: Reorganize DDR2 ECC handlingFelix Radensky2009-10-02-0/+4
| |/ | | | | | | | | | | | | | | | | | | Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
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