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* ppc4xx: ML507 Board SupportRicardo Ribalda Delgado2008-07-18-0/+116
| | | | | | | | | | | | | | | | | | | | | The Xilinx ML507 Board is a Virtex 5 prototyping board that includes, among others: -Virtex 5 FX FPGA (With a ppc440x5 in it) -256MB of SDRAM2 -32MB of Flash -I2C Eeprom -System ACE chip -Serial ATA connectors -RS232 Level Conversors -Ethernet Transceiver This patch gives support to a standard design produced by EDK for this board: ppc440, uartlite, xilinx_int and flash - Includes Changes propossed by Stefan Roese and Michal Simek Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: CPU PPC440x5 on Virtex5 FXRicardo Ribalda Delgado2008-07-18-0/+78
| | | | | | | | | | | -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-17-96/+534
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-07-15-0/+345
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| | * mpc5xxx: Add MVBC_P board supportAndre Schwarz2008-07-15-0/+345
| | | | | | | | | | | | | | | | | | | | | | | | The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet controller (using e1000) and custom Altera Cyclone-II FPGA on PCI. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-07-15-8/+8
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| | * | Update Freescale sys_eeprom.c to handle CCID formatsTimur Tabi2008-07-15-8/+8
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats. The NXID format replaces the older CCID format, but it's important to support both since most boards out there still use the CCID format. This change is in preparation for using one file to handle both formats. This will also unify EEPROM support for all Freescale 85xx and 86xx boards. Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR instead of ID_EEPROM_ADDR. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-07-15-83/+177
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| | * Clean up INIT_RAM optionsAndy Fleming2008-07-14-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The L2_INIT_RAM option was unused, and recent changes to the TLB code meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce the amount of mapped space attached to nothing, we change things so the TLBs get cleared. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Remove fake flash bank from 8544 DSAndy Fleming2008-07-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The fake flash bank was generating errors for anyone who didn't have a PromJET hooked up to the board. As that constitutes the vast majority of users, we remove it. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * MPC8544DS: Add ATI Video card supportKumar Gala2008-07-14-2/+22
| | | | | | | | | | | | | | | | | | Add support for using a PCIe ATI Video card on PCIe2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * 85xx: Add some L1/L2 SPR register definitionsKumar Gala2008-07-14-0/+20
| | | | | | | | | | | | | | | | | | Add new L1/L2 SPRs related to e500mc cache config and control. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8560: enable CONFIG_OF_LIBFDT by defaultPaul Gortmaker2008-07-14-0/+5
| | | | | | | | | | | | | | | | | | | | | Make the default build for the sbc8560 board be powerpc capable with libfdt support. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| | * Fix indentation for default boot environment variablesAndy Fleming2008-07-14-19/+19
| | | | | | | | | | | | | | | | | | | | | This was proposed by Paul Gortmaker in response to Wolfgang's comments on similar #defines in sbc8560.h. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * sbc8560: add default fdt valuesPaul Gortmaker2008-07-14-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add in the default fdt settings and the typical EXTRA_ENV settings as borrowed from the mpc8560ads. Fix a couple of stale references to the mpc8560ads dating back to the original clone/fork. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * sbc8560: define eth0 and eth1 instead of eth1 and eth2Paul Gortmaker2008-07-14-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing config doesn't define CONFIG_HAS_ETH0, and so the fdt support doesn't update the zeros in the dtb local-mac with real data from the u-boot env. Since the existing config is tailored to just two interfaces, get rid of the ETH2 definitions at the same time. Also don't include any end user specific data into the environment by default -- things like MAC address, network parameters etc. need to come from the end user. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * sbc8560: proper definitions for TSEC.Paul Gortmaker2008-07-14-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions for the TSEC have become out of date. There is no longer any such options like "CONFIG_MPC85xx_TSEC1" or similar. Update to match those of other boards, like the MPC8560ADS. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
| | * fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips2008-07-14-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * Remove LBC_CACHE_BASE from 8544 DSAndy Fleming2008-07-14-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Fix some more printf() format issues.Wolfgang Denk2008-07-13-5/+4
| |/ | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-14-726/+18
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| * hwmon: rename CONFIG_DS1722 to CONFIG_DTT_DS1722Michal Simek2008-07-13-1/+1
| | | | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefan Roese <sr@denx.de>
| * hwmon: Cleaning hwmon devicesMichal Simek2008-07-13-75/+2
| | | | | | | | | | | | | | | | Clean Makefile Move device specific values to driver for better reading Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefan Roese <sr@denx.de>
| * microblaze: Remove useless ancient headersMichal Simek2008-07-13-645/+0
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Clean uartlite driverMichal Simek2008-07-13-0/+2
| | | | | | | | | | | | | | | | Redesign uartlite driver to in_be32 and out_be32 macros Fix missing header in io.h Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Grant Likely <grant.likely@secretlab.ca>
| * Enable passing of ATAGs required by latest Linux kernel.Marcel Ziswiler2008-07-13-0/+4
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| * ARM: Fix for broken compilation when defining CONFIG_CMD_ELFHugo Villeneuve2008-07-13-0/+1
| | | | | | | | | | | | caused by missing dcache status/enable/disable functions. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2008-07-13-5/+7
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| | * Fix compile error caused by missing timer functionTsiChung Liew2008-07-11-0/+2
| | | | | | | | | | | | | | | | | | Add #define CONFIG_MCFTMR in EB+MCF-EV123.h configuration file Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| | * ColdFire: Fix timer issue for MCF5272TsiChung Liew2008-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | The timer was assigned to wrong timer memory mapped which caused udelay() and timer() not working properly. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| | * ColdFire: Fix code flash configuration for M547x/M548x boardsTsiChung Liew2008-07-11-4/+4
| | | | | | | | | | | | Signed-off-by: Kurt Mahan <kmahan@freescale.com>
| * | DataFlash AT45DB021 supportSergey Lapin2008-07-10-0/+1
| |/ | | | | | | | | | | | | | | | | Some boards based on AT91SAM926X-EK use smaller DF chips to keep bootstrap, u-boot and its environment, using NAND or other external storage for kernel and rootfs. This patch adds support for small 1024x263 chip. Signed-off-by: Sergey Lapin <slapin@ossfans.org>
* | ppc4xx: Some Rewood cleanups (coding style, leading white spaces)Stefan Roese2008-07-11-6/+6
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add 460SX UIC definesStefan Roese2008-07-11-1/+21
| | | | | | | | | | | | Only the really needed ones are added (cascading and EMAC/MAL). Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Continue cleanup of ppc440.hStefan Roese2008-07-11-302/+3
| | | | | | | | | | | | | | This patch continues the ppc440.h cleanup by removing some of the unused defines. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Cleanup Katmai & Yucca PCIe register usageStefan Roese2008-07-11-1/+0
| | | | | | | | | | | | | | This patch cleans up the 440SPe PCIe register usage. Now only defines from the include/asm-ppc/4xx_pcie.h are used. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Rework 440GX UIC handlingStefan Roese2008-07-11-46/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-1368/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-28/+24
| | | | | | | | | | | | | | | | | | This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx EBC definesStefan Roese2008-07-11-201/+157
| | | | | | | | | | | | | | | | | | | | | | This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add MII mode support to the EMAC RGMII BridgeGrant Erickson2008-07-11-1/+17
| | | | | | | | | | | | | | | | | | This patch adds support for placing the RGMII bridge on the PPC405EX(r) into MII/GMII mode and allows a board-specific configuration to specify the bridge mode at compile-time. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM ControllerGrant Erickson2008-07-11-76/+336
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM controller registers (MODT and INITPLR) used by the PowerPC405EX(r). The MMODE and MEMODE registers are unified with their peer values used for the INITPLR MR and EMR registers, respectively. Finally, a spelling typo is correct (MANUEL to MANUAL). With these mnemonics in place, the CFG_SDRAM0_* magic numbers for Kilauea are replaced by equivalent mnemonics to make it easier to compare and contrast other 405EX(r)-based boards (e.g. during board bring-up). Finally, unified the SDRAM controller register dump routine such that it can be used across all processor variants that utilize the IBM DDR2 SDRAM controller core. It produces output of the form: PPC4xx IBM DDR2 Register Dump: ... SDRAM_MB0CF[40] = 0x00006701 ... which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included since it is not uncommon that the DCR values in header files get mixed up and it helps to validate, at a glance, they match what is printed in the user manual. Tested on: AMCC Kilauea/Haleakala: - NFS Linux Boot: PASSED - NAND Linux Boot: PASSED Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add AMCC/IBM DDR2 SDRAM ECC Field MnemonicsGrant Erickson2008-07-11-0/+52
| | | | | | | | | | | | | | | | | | Add additional DDR2 SDRAM memory controller DCR mneomnics, condition revision ID DCR based on 405EX, and add field mnemonics for bus error status and ECC error status registers. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add SDR0_SRST Mnemonics for the 405EX(r)Grant Erickson2008-07-11-0/+36
| | | | | | | | | | | | | | This patch adds bit field mnemonics for the 405EX(r) SDR0_SRST soft reset register. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)Grant Erickson2008-07-11-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value. Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add initial 460SX reference board (redwood) config file and defines.Feng Kan2008-07-11-9/+207
|/ | | | | Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc512xWolfgang Denk2008-07-10-7/+32
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| * Configuration changes for ADS5121 Rev 3Martha Marx2008-07-10-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADS5121 Rev 3 board is now the default config config targets are now ads5121_config Rev 3 board with PCI M41T62 on board RTC 512MB DRAM ads5121_rev2_config Rev 2 board with No PCI 256MB DRAM Signed-off-by: Martha Marx <mmarx@silicontkx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: John Rigby <jrigby@freescale.com>
| * Consolidate ADS5121 IO Pin configurationMartha Marx2008-07-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | Consolidate ADS5121 IO Pin configuration to one file board/ads5121/iopin.c. Remove pin config from cpu/mpc512x/fec.c Signed-off-by: Martha Marx <mmarx@silicontkx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: John Rigby <jrigby@freescale.com>
* | Merge commit 'wd/master'Jon Loeliger2008-07-10-235/+396
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