summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeLines
* ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-0/+8
| | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: sc3: Remove unreferenced external declarations from sc3.hStefan Roese2009-11-02-5/+0
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mpc52xx: add support for the IPEK01 boardWolfgang Grandegger2009-10-31-0/+408
| | | | | | | This patch adds support for the board IPEK01 based on the MPC5200. The Futjitsu Lime graphics controller is configured in 16 bpp mode. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* Merge branch 'next' of git://git.denx.de/u-boot-video into nextWolfgang Denk2009-10-31-6/+18
|\
| * video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01Wolfgang Grandegger2009-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words for D32 accesses due to the diffferent connecting to the GDC bus. This patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP, which should be set for all board using the mb862xx in 16 bpp mode. For the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp modeAnatolij Gustschin2009-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | The new IPEK01 board can use the 32 bpp mode for the Lime graphics controller. For this mode, video accelaration does not work. This patch makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL, which is enabled for the lwmon5 and the socrates board for backward compatibility. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * video: mb862xx: improve board-specific Lime configurationWolfgang Grandegger2009-10-31-6/+14
| | | | | | | | | | | | | | | | | | | | | | To avoid board-specific code accessing the mb862xx registers directly, the public function mb862xx_probe() has been introduced. Furthermore, the "Change of Clock Frequency" and "Set Memory I/F Mode" registers are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR, respectively. The BSPs for the socrates and lwmon5 boards have been adapted accordingly. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* | new PCA9564 i2c bridge driverValentin Yakovenkov2009-10-30-0/+50
|/ | | | | Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-10-28-0/+157
|\
| * cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
* | Fix Compliation warning for TNY-A9260 and TNY-A9G20Sandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Fix Compliation warning for SBC35-A9G20 boardSandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | galaxy5200: Add default environment variablesEric Millbrandt2009-10-28-2/+8
|/ | | | | | | Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add 'editenv' commandPeter Tyser2009-10-27-0/+2
| | | | | | | | | The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-10-27-1/+59
|\
| * mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+23
| | | | | | | | | | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * xpedite5370: Enable multi-core supportPeter Tyser2009-10-27-0/+8
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Revert "env: only build env_embedded and envcrc when needed"Wolfgang Denk2009-10-27-5/+0
|/ | | | | | Breaks building on many boards, and no really clean fix available yet. This reverts commit 6dab6add2d8ee80905234b326abc3de11be1d178.
* Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-10-24-1215/+1763
|\
| * s5pc1xx: SMDKC100: fix compile warningsMinkyu Kang2009-10-24-112/+112
| | | | | | | | | | | | | | fix the following compile warnings warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * TI OMAP3 SDP3430: Initial SupportTom Rix2009-10-24-0/+369
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start of support of Texas Instruments Software Development Platform(SDP) for OMAP3430 - SDP3430 Highlights of this platform are: Flash Memory devices: Sibley NOR, Micron 8bit NAND and OneNAND Connectivity: 3 UARTs and expanded 4 UART ports + IrDA Ethernet, USB Other peripherals: TWL5030 PMIC+Audio+Keypad VGA display Expansion ports: Memory devices plugin boards (PISMO) Connectivity board for GPS,WLAN etc. Completely configurable boot sequence and device mapping etc. Support default jumpering and: - UART1/ttyS0 console(legacy sdp3430 u-boot) - UART3/ttyS2 console (matching other boards, and SDP HW docs) - Ethernet - mmc0 - NOR boot Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9. Conflicts: Makefile Fixed the conflict with smdkc100_config by moving omap_sdp3430_config to it is alphabetically sorted location above zoom1. Signed-off-by: David Brownell <david-b@pacbell.net> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * TI DaVinci: Adding Copyright for DM365 EVMSandeep Paulraj2009-10-24-0/+1
| | | | | | | | | | | | | | Forgot to add Copyright while submitting the patch. This patch adds the copyright. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci: Fix DM6467 EVM Compilation WarningSandeep Paulraj2009-10-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI OMAP3: make gpmc_config as constNishanth Menon2009-10-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP3: export enable_gpmc_cs_config to board filesNishanth Menon2009-10-18-0/+2
| | | | | | | | | | | | | | | | | | Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config' Signed-off-by: Nishanth Menon <nm@ti.com>
| * TI DaVinci Sonata: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DVEVM: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DM365: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DM355: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI: OMAP3: Remove SZ_xx referencesSandeep Paulraj2009-10-18-56/+49
| | | | | | | | | | | | | | This patch removes dependency on the sizes.h header file and removes all references to SZ_xx. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * OMAP3: Update Overo and Beagle environmentSteve Sakoman2009-10-18-16/+38
| | | | | | | | | | | | | | | | Update default environment to support new kernel DSS2 subsystem and simplify rootfs type and location changes. Signed-off-by: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * TI: DaVinci: DM355 Leopard board supportSandeep Paulraj2009-10-18-0/+162
| | | | | | | | | | | | | | This patch adds support for the leopard board which is based on the DM355 SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DM646x: Adding initial support for DM6467 EVMSandeep Paulraj2009-10-18-0/+132
| | | | | | | | | | | | | | This patch adds the initial support for DM6467 EVM. Other features like NET and NAND support will be added as follow up patches. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * AT91 CPUAT91 Fix compiler warningEric Benard2009-10-18-2/+2
| | | | | | | | | | | | | | | | | | | | This change fixes the compiler warning main.c: In function 'abortboot': main.c:122: warning: too few arguments for format Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * AT91 CPU9260 CPU9G20 Fix compile warningsEric Benard2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | This change fixes the compiler warning nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * Clean-up of s3c24x0 header fileskevin.morfitt@fearnside-systems.co.uk2009-10-13-1121/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the arm920t s3c24x0 header files in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patch 1/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boardskevin.morfitt@fearnside-systems.co.uk2009-10-13-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and s3c2410 cpu's which fixes various problems such as the timeouts in tftp being too short. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. It was originally submitted on 21/06/2009 but didn't get into the 2009.08 release, and Jean-Pierre made one comment on the original patch (see http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two changes to the original patch: - it's been re-based to the current release - I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it directly to the maintainers of all except the sbc2410 which doesn't have an entry in MAINTAINERS. Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain> Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * s5pc1xx: add support SMDKC100 boardMinkyu Kang2009-10-13-0/+242
| | | | | | | | | | | | | | Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
| * s5pc1xx: support serial driverMinkyu Kang2009-10-13-0/+7
| | | | | | | | | | | | | | | | This patch includes the serial driver for s5pc1xx. s5pc1xx uart driver needs own register setting and clock configuration. So, need to special driver. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * s5pc1xx: support onenand driverMinkyu Kang2009-10-13-0/+136
| | | | | | | | | | | | | | This patch includes the onenand driver for s5pc100 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * s5pc1xx: support Samsung s5pc1xx SoCMinkyu Kang2009-10-13-0/+475
| | | | | | | | | | | | | | | | This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-10-24-1/+18
|\ \
| * | ppc4xx: Sequoia: Add chip_config commandStefan Roese2009-10-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add function to check and dynamically change PCI sync clockStefan Roese2009-10-23-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update flash size in reg property of the NOR flash nodeStefan Roese2009-10-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now only the ranges in the ebc node are updated with the values currently configured in the PPC4xx EBC controller. With this patch now the NOR flash size is updated in the device tree blob as well. This is done by scanning the compatible nodes "cfi-flash" and "jedec-flash" for the correct chip select number. This size fixup is enabled for all AMCC eval board right now. Other 4xx boards may want to enable it as well, if this problem with multiple NOR FLASH sizes exists. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * | fdt: Add fdt_fixup_nor_flash_size() to fixup NOR FLASH size in dtbStefan Roese2009-10-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be used to update the size in the "reg" property of the NOR FLASH device nodes. This is necessary for boards with non-fixed NOR FLASH sizes. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Wolfgang Denk <wd@denx.de>
generated by cgit v1.1 at 2024-12-21 10:04:04 +0000