| Commit message (Collapse) | Author | Age | Lines |
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This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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Remove this tab from env, since it's useless, just use spaces.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Remove this tab from env, since it's useless, just use spaces.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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PERST_GPIO and POWER_GPIO are currently swapped.
Fix the GPIO assignments as per the board schematics.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Select CONFIG_CMD_FUSE so that the fuse API commands can be used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable the CONFIG_CMD_FS_GENERIC on m53evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Enable the CONFIG_CMD_FS_GENERIC on m28evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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1. Set the image load partition to the first FAT partition.
2. Set the kernel rootfs partition to the second partition.
Signed-off-by: Ye.Li <B37916@freescale.com>
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To support loading FDT file for kernel, add the fdt address,
file and loading script to arm2 board default environment.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related
to generic board support is not in place.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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We should pass the MMC1 base address into CONFIG_SYS_FSL_ESDHC_ADDR.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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on Sabrelite board
Sabrelite board has two solts: 0 is SD3 (bottom) slot and 1 is uSD4 (top) slot.
This patch makes use of both slots instead of only one.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
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This patch adds boot script support to am335x_evm
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
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and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'.
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
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Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Copy them from Linux v3.16 tag.
My main motivation of this commit is to add compiler-clang.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
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update to provide usable implementation to U-Boot
Signed-off-by: Steve Rae <srae@broadcom.com>
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U-Boot has imported various source files from other projects,
mostly Linux.
Something like
#ifdef __UBOOT__
[ modification for U-Boot ]
#else
[ original code ]
#endif
is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.
Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
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Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
Also add a binding file since this is missing.
Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add driver model support so that ns16550 can support operation both with
and without driver model.
The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move the function that calculates the baud rate divisor into ns16550.c so
it can be used by that file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Allow the caller to find out the device that was bound in response to this
call.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Allocate 1KB so that driver model can operate before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
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For some boards board_init() will change GPIOs, so we need to have driver
model available before then. Adjust the board init to arrange this, but
enable it for driver model only, just to be safe.
This does create additional #ifdef logic, but it is safer than trying to
make a pervasive change which may cause some boards to break.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The microblaze-generic board fails to build at least
with the kernel.org crosstool:
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz
$ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all
[ snip ]
CC disk/part.o
CC disk/part_dos.o
LD disk/built-in.o
CC drivers/block/systemace.o
{standard input}: Assembler messages:
{standard input}:2495: Error: operation combines symbols in different segments
{standard input}:2496: Error: operation combines symbols in different segments
{standard input}:2499: Error: operation combines symbols in different segments
{standard input}:2500: Error: operation combines symbols in different segments
{standard input}:2505: Error: operation combines symbols in different segments
{standard input}:2506: Error: operation combines symbols in different segments
{standard input}:2515: Error: operation combines symbols in different segments
{standard input}:2516: Error: operation combines symbols in different segments
{standard input}:2519: Error: operation combines symbols in different segments
{standard input}:2520: Error: operation combines symbols in different segments
{standard input}:2529: Error: operation combines symbols in different segments
{standard input}:2530: Error: operation combines symbols in different segments
{standard input}:2533: Error: operation combines symbols in different segments
{standard input}:2534: Error: operation combines symbols in different segments
{standard input}:2539: Error: operation combines symbols in different segments
{standard input}:2540: Error: operation combines symbols in different segments
{standard input}:2549: Error: operation combines symbols in different segments
{standard input}:2550: Error: operation combines symbols in different segments
make[3]: *** [drivers/block/systemace.o] Error 1
make[2]: *** [drivers/block] Error 2
make[1]: *** [drivers] Error 2
make: *** [__build_one_by_one] Error 2
It looks like the cause of this error message is the "#ident" directive.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
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This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
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Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for instance.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
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LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
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For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
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