| Commit message (Collapse) | Author | Age | Lines |
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Signed-off-by: Tom Rini <trini@ti.com>
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Add a DT simple-framebuffer node to DT when booting the Linux kernel.
This will allow the kernel to inherit the framebuffer configuration from
U-Boot, and display a graphical boot console, and even run a full SW-
rendered X server.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
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simple-framebuffer is a new device tree binding that describes a pre-
configured frame-buffer memory region and its format. The Linux kernel
contains a driver that supports this binding. Implement functions to
create a DT node (or fill in an existing node) with parameters that
describe the framebuffer format that U-Boot is using.
This will be immediately used by the Raspberry Pi board in U-Boot, and
likely will be used by the Samsung ARM ChromeBook support soon too. It
could well be used by many other boards (e.g. Tegra boards with built-in
LCD panels, which aren't yet supported by the Linux kernel).
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
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The location of valid scratch space is dependent on SoC, so move that
there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On
am33xx/ti814x we want to use what the ROM defines as "public stack"
which is the area after our defined download image space. Correct the
comment about and location of CONFIG_SPL_TEXT_BASE.
Signed-off-by: Tom Rini <trini@ti.com>
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Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used. As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.
Signed-off-by: Tom Rini <trini@ti.com>
---
Changes in v2:
- Fix typo noted by Peter Korsgaard
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This patch does a similar code reogranzation from
http://patchwork.ozlabs.org/patch/132179/
which is based on an old version of code (fdt support and bus selection
still not in). It merges this tidy-up on top of the recent code. It does
not make any logical change.
tpm.c implements the interface defined in tpm.h based on underlying
LPC or I2C TPM driver. tpm.c and the underlying driver communicate
throught tpm_private.h.
Note: Merging the LPC driver with tpm.c is left to future patches.
Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs,
which supports clockstretching, combined reads and a bus speed of
up to 400khz. The device also has a new device id.
This is based on the kernel patch provided by Infineon :
https://gerrit.chromium.org/gerrit/42332
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
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The new name is more aligned with Linux kernel's naming of TPM driver.
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Now that the code for loading these three images from a FIT is common, we
don't need individual boostage IDs for each of them.
Note: there are some minor changes in the bootstage numbering, particuarly
for kernel loading. I don't believe this matters.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Use the new common code to load a kernel. The functionality should not
change.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Use the new common code to load a flat device tree. Also fix up a few casts
so that this code works with sandbox. Other than that the functionality
should not change.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Use the new common code to load a ramdisk. The functionality should not
change.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present code to load an image from a FIT is duplicated in the three
places where it is needed (kernel, fdt, ramdisk).
The differences between these different code copies is fairly minor.
Create a new function in the fit code which can handle any of the
requirements of those cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Loading a ramdisk, kernel or FDT goes through similar stages. Create
a block of IDs for each task, and define a consistent numbering within
the block. This will allow use of common code for image loading.
Signed-off-by: Simon Glass <sjg@chromium.org>
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There are two implementations of abortboot(). Turn these into two separate
functions, and create a single abortboot() which calls either one or the
other.
Also it seems that nothing uses abortboot() outside main, so make it static.
At this point there is no further use of CONFIG_MENU in main.c.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
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This function should be declared in net.h.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
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This is not currently used, since autoboot is not enabled for this
board, but the string is missing a parameter. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.
- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).
To produce this update I used tag v3.7.1 of linux-stable repository.
The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
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Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.
Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Provided a default RCW for P5040, then it can use PBL to build
ramboot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.
Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
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Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.
It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC
variants supported on the same board.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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T4240QDS uses a SST instead of SPANSION SPI flash.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.
Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
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This seems to be a common function for several architectures, so create
a common function rather than duplicating the code in each arch.
Also make an attempt to avoid introducing #ifdefs in the new code, partly
by removing useless #ifdefs around function declarations in the image.h
header.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This code is very large, and in SPL it isn't always useful to print
out image information (in fact there might not even be a console
active). So disable this feature unless this option is set.
Signed-off-by: Simon Glass <sjg@chromium.org>
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There are only two left. One is unnecessary and the other can be moved
to the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Much of the image code uses addresses as ulongs and pointers interchangeably,
casting between the two forms as needed.
This doesn't work with sandbox, which has a U-Boot RAM buffer which is
separate from the host machine's memory.
Adjust the cost so that translating from a U-Boot address to a pointer uses
map_sysmem(). This allows bootm to work correctly on sandbox.
Note that there are no exhaustive tests for this code on sandbox, so it is
possible that some dark corners remain.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de> (v1)
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This function will be used to print signatures as well as hashes, so rename
it. Also make it static since it is not used outside this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
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We intend to add signatures to FITs also, so rename this function so that
it is not specific to hashing. Also rename fit_image_set_hashes() and
make it static since it is not used outside this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
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This function will be needed by signature checking code, so export it,
and also add docs.
Signed-off-by: Simon Glass <sjg@chromium.org>
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