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* powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-53/+1
| | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fm-eth: add function fm_info_get_phy_address()Timur Tabi2012-08-23-0/+1
| | | | | | | | | Function fm_info_get_phy_address() returns the PHY address for a given Fman port. This is handy when the MDIO code needs to fixup the Ethernet nodes in the device tree to point to PHY nodes for a specific PHY address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+1
| | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/CoreNet: add tool to support pbl image build.Shaohui Xie2012-08-23-0/+9
| | | | | | | | | | Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Slave module for boot from PCIELiu Gang2012-08-23-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Master module for boot from PCIELiu Gang2012-08-23-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-6/+0
| | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-26/+65
| | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mtd/cfi_flash: fix write problems for Numonyx P33/30 32 MBit flashsHolger Brunck2012-08-13-0/+1
| | | | | | | | | | | | | | | | | | commit 54652991 Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads to problems for smaller versions of this chip e.g. the 32Mbit version with deviceid 0x16 on mgcoge. So move the code for this work around to an own function and check previously manufacturer id and device id to not break other flashes which don't need this work around. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Heiko Schocher <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Philippe De Muyter <phdm@macqel.be> cc: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: add support for Spansion flash PPB sector protectionAnatolij Gustschin2012-08-13-0/+7
| | | | | | | | | | Erasing flash sectors protected with persistent protection bit (PPB) mechanism on Spansion flash chips doesn't work. Add sector protection status checking and sector lock and unlock commands to fix this. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* zfs: Add ZFS filesystem supportJorgen Lundman2012-08-09-0/+1571
| | | | | | | | | | | | | | | | | | | | | U-Boot port is based on sources forked from GRUB-0.97 by Sun in 2004, which can be found here: http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/grub/grub-0.97/stage2/zfs-include/zfs.h Released by Sun for GRUB under the license: * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. GRUB official releases include ZFS in version: ftp://alpha.gnu.org/gnu/grub/grub-1.99~rc1.tar.gz And patched against GRUB Bazaar repository for ashift fixes (4KB HDDs) more conveniently found at github: https://github.com/pendor/grub-zfs/commit/e7b6ef3ac3b9685ac4c394c897b1d4221b7381f1 Signed-off-by: Jorgen Lundman <lundman@lundman.net>
* rename EB+MCF-EV123 to its current marketing name EB+CPU5282Jens Scharsig2012-08-09-5/+5
| | | | | | | | | * rename board directory to eb_cpu5282 * rename EB+MCF-EV123_.*config to eb_cpu5282_.*config * add Maintainer for EB+CPU5282 board * rename prompt Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
* configs: Remove unused symbol CONFIG_DISCOVER_PHYFabio Estevam2012-08-09-10/+0
| | | | | | CONFIG_DISCOVER_PHY is not used anywhere, so remove it from config files. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Add run_command_list() to run a list of commandsSimon Glass2012-08-09-0/+13
| | | | | | | | | This new function runs a list of commands separated by semicolon or newline. We move this out of cmd_source so that it can be used by other code. The PXE code also uses the new function. Suggested-by: Michael Walle <michael@walle.cc> Signed-off-by: Simon Glass <sjg@chromium.org>
* Malloc: Fix -Wundef warningsMarek Vasut2012-08-09-3/+3
| | | | | | | | | | In file included from arch/arm/lib/board.c:43:0: include/malloc.h:490:5: warning: "HAVE_MMAP" is not defined [-Wundef] include/malloc.h:590:5: warning: "HAVE_USR_INCLUDE_MALLOC_H" is not defined [-Wundef] include/malloc.h:757:5: warning: "HAVE_MMAP" is not defined [-Wundef] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
* global_data: unify global flag definesMike Frysinger2012-08-09-0/+28
| | | | | | | All the global flag defines are the same across all arches. So unify them in one place, and add a simple way for arches to extend for their needs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-08-09-24/+72
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs powerpc/mpc85xx: Ignore E bit for BSC9130/1 powerpc/sgmii: To support PHY link state auto detect in SGMII mode powerpc/85xx: improve definition of BR_PHYS_ADDR macro powerpc/p2041: configure the CPLD lane_mux according to RCW powerpc/ddr: fix fsl_ddr_get_dimm_params compile error powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB powerpc/p1022ds: fix DIU/LBC switching with NAND enabled powerpc/p1022ds: add support for SPI and SD boot Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc/85xx: improve definition of BR_PHYS_ADDR macroTimur Tabi2012-08-08-20/+18
| | | | | | | | | | | | | | | | The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is definedShaohui Xie2012-08-08-1/+6
| | | | | | | | | | | | | | | | | | | | ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined and non-NOR u-boot is building, it will cause compile error. Also, add CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash write performance. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/p1022ds: add support for SPI and SD bootMatthew McClintock2012-08-08-3/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | sh: Add support pin function control using GPIONobuhiro Iwamatsu2012-08-08-0/+192
|/ | | | | | | | Renesas SH and R-Mobile set up device using PFC. This provide the framework. Most codes were brought from linux kernel. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* powerpc/82xx: adapt SDRAM settings for mgcoge3neGerlando Falauto2012-07-31-2/+4
| | | | | | | | | | The HW guys suggested to change these two values. And these values are now identical to the values we use on mgcoge. PSDMR_WRC was set to 1C as it should lead to better performance. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* powerpc/82xx: use SDRAM detection for mgcoge2neGerlando Falauto2012-07-31-4/+13
| | | | | | | | | | | | | | mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same u-boot we use here the SDRAM detection. This patch enables SDRAM detection between 256MB and 128MB. So in addition to the existing 256MB geometry: 4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks we can now also have 128MB geometry: 4 chips x 4M (13 rows, 9 cols) x 16 bit x 4 banks Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: move km/km82xx-common.h within km82xx.hGerlando Falauto2012-07-31-318/+289
| | | | | | | The only file including km82xx-common.h is km82xx.h. So there is no need to have it as a separate file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: merge mgcoge.h and mgcoge3ne.h into km82xx.hGerlando Falauto2012-07-31-94/+57
| | | | | | | | | Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need to keep them as separate .h config files. Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h file. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: move mgcoge, mgcoge3ne defines to ease subsequent mergeGerlando Falauto2012-07-31-34/+34
| | | | Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* powerpc/82xx: remove unused define for mgcoge3neHolger Brunck2012-07-31-3/+0
| | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-07-31-4/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: km/common: remove printfs for i2c deblocking code CONFIG: SMDK5250: I2C: Enable I2C I2C: Add support for Multi channel I2C: Modify the I2C driver for EXYNOS5 I2C: Move struct s3c24x0_i2c to a common place. EXYNOS: PINMUX: Add pinmux support for I2C EXYNOS5: define EXYNOS5_I2C_SPACING EXYNOS: Add I2C base address. EXYNOS: CLK: Add i2c clock mx6qsabrelite: add i2c multi-bus support imx-common: add i2c.c for bus recovery support i.mx53: add definition for I2C3_BASE_ADDR i.mx: iomux-v3.c: move to imx-common directory i.mx: iomux-v3.h: move to imx-common include directory iomux-v3: remove include of mx6x_pins.h mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support mxc_i2c: add bus recovery support mxc_i2c: prep work for multiple busses support mxc_i2c: add i2c_regs argument to i2c_imx_stop mxc_i2c: add retries mxc_i2c: check for arbitration lost mxc_i2c: change slave addr if conflicts with destination. mxc_i2c: don't disable controller after every transaction mxc_i2c: place i2c_reset code inline mxc_i2c: place imx_start code inline mxc_i2c: remove redundant read mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state mxc_i2c.c: code i2c_probe as a 0 length i2c_write mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write mxc_i2c: create i2c_init_transfer mxc_i2c: clear i2sr before waiting for bit mxc_i2c: create tx_byte function mxc_i2c: remove ifdef of CONFIG_HARD_I2C mxc_i2c: fix i2c_imx_stop i2c: deblock i2c bus also if accessed before realocation Signed-off-by: Wolfgang Denk <wd@denx.de>
| * CONFIG: SMDK5250: I2C: Enable I2CRajeshwari Shinde2012-07-31-0/+10
| | | | | | | | | | | | | | | | | | | | | | This enables I2C support on smdk5250. Pinmux setting moved to board file to avoid repeated setting of gpio lines. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mx6qsabrelite: add i2c multi-bus supportTroy Kisky2012-07-31-4/+2
| | | | | | | | | | | | | | This includes bus recovery support. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2012-07-31-16/+113
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Wire up SPI driver spi: microblaze: Adds driver for Xilinx SPI controller microblaze: intc: Clear interrupt code microblaze: Call serial multi initialization microblaze: Move __udelay implementation microblaze: Remove extern from board.c microblaze: Wire up dts configuration fdt: Add board specific dts inclusion microblaze: Move individual board linker scripts to common script in cpu tree. microblaze: Add gpio.h microblaze: Add missing undefs for UBI and UBIFS microblaze: Expand and correct configuration comments microblaze: Enable ubi support microblaze: Avoid compile error on systems without cfi flash microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * microblaze: Wire up SPI driverStephan Linz2012-07-31-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | Depending on XILINX_SPI_FLASH_BASEADDR enable SPI flash and environment in SPI flash. Expected values from xparameters.h are: - XILINX_SPI_FLASH_BASEADDR - XILINX_SPI_FLASH_MAX_FREQ - XILINX_SPI_FLASH_CS Signed-off-by: Stephan Linz <linz@li-pro.net> Acked-by: Michal Simek <monstr@monstr.eu>
| * microblaze: intc: Clear interrupt codeMichal Simek2012-07-10-1/+0
| | | | | | | | | | | | | | | | | | Clear and prepare for device-tree driven configuration. Remove CONFIG_SYS_INTC_0 definition Use dynamic allocation instead of static. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Simon Glass <sjg@chromium.org>
| * microblaze: Wire up dts configurationStephan Linz2012-07-10-0/+5
| | | | | | | | | | | | | | | | | | - enable OF control and embedded OF - set default device tree file name to 'microblaze' - add CPP to dtc proxy: board/xilinx/dts/microblaze.dts - add an empty but processable dts for microblaze-generic Signed-off-by: Stephan Linz <linz@li-pro.net>
| * microblaze: Add missing undefs for UBI and UBIFSStephan Linz2012-07-09-0/+2
| | | | | | | | | | | | | | In the case of missing flash usage disaple (undef) all the UBI support in the same way as for JFFS2. Signed-off-by: Stephan Linz <linz@li-pro.net>
| * microblaze: Expand and correct configuration commentsStephan Linz2012-07-09-7/+29
| | | | | | | | | | | | | | | | | | | | | | | | - fix CONFIG_SYS_MALLOC_BASE from 0x11FB_F000 to 0x13EF_F000 - add new size calculation for CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_MALLOC_LEN derived from SIZE - change CONFIG_SYS_MONITOR_BASE and CONFIG_SYS_MALLOC_BASE calculation to a symbolic equation with the corresponding _LEN definitions - add a "CFI flash memory layout - Example" comment Signed-off-by: Stephan Linz <linz@li-pro.net>
| * microblaze: Enable ubi supportStephan Linz2012-06-27-2/+18
| | | | | | | | | | | | | | | | | | Increase malloc area for UBI to >= 512k -- foreseeing of UBIFS set to 768k. To save memory in flash (CONFIG_SYS_MONITOR_LEN) the UBIFS is disabled by default. Signed-off-by: Stephan Linz <linz@li-pro.net> Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Avoid compile error on systems without cfi flashStephan Linz2012-06-27-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Use XILINX_FLASH_START to set/unset FLASH and RAMENV. Error: board.c: In function 'board_init': board.c:134: error: 'XILINX_FLASH_START' undeclared (first use in this function) board.c:134: error: (Each undeclared identifier is reported only once board.c:134: error: for each function it appears in.) Signed-off-by: Stephan Linz <linz@li-pro.net> Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTIONStephan Linz2012-06-27-2/+0
| | | | | | | | | | | | | | | | | | CONFIG_SYS_FLASH_PROTECTION is defined twice. The second one is outside the flash configuration context and we can remove it safely. Signed-off-by: Stephan Linz <linz@li-pro.net> Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'next' of git://git.denx.de/u-bootWolfgang Denk2012-07-30-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot: MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c doc: cleanup - move board READMEs into respective board directories net: sh_eth: add support for SH7757's GETHER net: sh_eth: modify the definitions of regsiter net: sh_eth: add SH_ETH_TYPE_ condition net: sh_eth: clean up for the SH7757's code net: fec_mxc: Fix MDC for xMII net: fec_mxc: Fix setting of RCR for xMII net: nfs: make NFS_TIMEOUT configurable net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| * \ Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk2012-07-12-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-net: net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | net: phy: micrel: make ksz9021 phy accessibleTroy Kisky2012-07-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micrel accidentally used the same part number for the KS8721 and KSZ9021. So, both cannot be in the same build of u-boot. Add a config option to handle this. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com>
* | | | hawkboard: Fix SPL Nand driver misconfigurationLinu Cherian2012-07-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hawkboard was using the wrong nand_read_page version for SPL image. As a side effect, the u-boot image loaded by the SPL from nand was getting corrupted. Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST to select the correct nand_read_page algorithm for SPL. Signed-off-by: Linu Cherian <linucherian@gmail.com> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Acked-by: Tom Rini <trini@ti.com>
* | | | common.h: Remove include compiler.hMarek Vasut2012-07-20-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove this as including it on global scale breaks a lot of things. This was reported by: Matthew McClintock <B29882@freescale.com> Fix found by: Tom Rini <trini@ti.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-07-20-3/+28
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: usb_storage: fix ehci driver max transfer size smsc95xx: align buffers to cache line size ehci-hcd: change debug() to printf() in case of errors usb: check return value of submit_{control, bulk}_msg usb: pass cache-aligned buffer to usb_get_descriptor() ehci-hcd: fix external buffer cache handling ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment ehci-hcd: program asynclistaddr before every transfer common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER ehci-omap: Do not call dcache_off from omap_ehci_hcd_init Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignmentTom Rini2012-07-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB spec says that 32 bytes is the minimum required alignment. However on some platforms we have a larger minimum requirement for cache coherency. In those cases, use that value rather than the USB spec minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here as we are not allowed to have tests inside of align(...). Signed-off-by: Tom Rini <trini@ti.com> [marek.vasut]: introduce some crazy macro voodoo Signed-off-by: Marek Vasut <marex@denx.de> [ilya.yanok]: moved external buffer fixes to separate patch, we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN for qh_list, qh and qtd structures to make sure they are proper aligned for both controller and cache operations. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | | common.h: Introduce DEFINE_CACHE_ALIGN_BUFFERMarek Vasut2012-07-18-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the out-of-function-scope counterpart of ALLOC_CACHE_ALIGN_BUFFER. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> [ilya.yanok]: added missing <linux/compiler.h> include and {DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment specification. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | | | | Blackfin: easylogo: add lzma logosMike Frysinger2012-02-03-0/+11
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bf527-ezkit boards are getting too big to fit into their reserved flash space, so we need to use a lzma compressed logo. Since the video driver code is very similar, add lzma compressed support to all of the Blackfin video drivers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | | Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk2012-07-18-3/+6
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam2012-07-10-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-12-16 22:25:57 +0000