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* Add Elpida Memory Configuration to mpc5121ads BoardsMartha M Stan2009-09-25-2/+33
| | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-44/+37
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-93/+488
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| * ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-09-24-0/+6
| | | | | | | | | | | | | | | | | | | | The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-2/+8
| | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-09-24-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-09-24-20/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * immap_85xx: add porpllsr's plat ratio definitionMingkai Hu2009-09-24-0/+2
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc85x0: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-24-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: allow enabling PCI via a make config optionPaul Gortmaker2009-09-24-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: update PCI/PCI-e support codePaul Gortmaker2009-09-24-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_pci: create a SET_STD_PCI_INFO() helper wrapperPaul Gortmaker2009-09-24-0/+12
| | | | | | | | | | | | | | | | Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: correct local bus SDRAM size from 64M to 128MPaul Gortmaker2009-09-24-4/+38
| | | | | | | | | | | | | | | | | | | | | | The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: enable access to second bank of flashPaul Gortmaker2009-09-24-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: delete unused MPC8548CDS info carried over from portPaul Gortmaker2009-09-24-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Clean up use of LAWAR definesKumar Gala2009-09-24-7/+2
| | | | | | | | | | | | | | | | | | On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for P1_P2_RDB boardsKumar Gala2009-09-24-0/+13
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for 36-bit config for P2020DSKumar Gala2009-09-24-0/+4
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DSKumar Gala2009-09-24-0/+4
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: simplify the top makefile for 36-bit config for mpc8536dsMingkai Hu2009-09-24-1/+1
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Fix LCRR_CLKDIV definesKumar Gala2009-09-24-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* | galaxy5200: enable version environment variableEric Millbrandt2009-09-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add version environment variable configuration to the galaxy5200 board header file. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com> Edited commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | digsy_mtc: Add TCR register value for RTC (DS1339)Werner Pfister2009-09-24-0/+1
|/ | | | | Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de> Signed-off-by: Detlev Zundel <dzu@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-10/+10
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| * ppc4xx: Make DDR2 timing for intip more robustDirk Eibach2009-09-23-10/+10
| | | | | | | | | | | | | | | | DDR2 timing for intip was on the edge for some of the available chips for this board. Now it is verfied to work with all of them. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc: Clean up calling of phy_reset() during initPeter Tyser2009-09-22-0/+17
| | | | | | | | | | | | | | Remove board-specific #ifdefs for calling phy_reset() during initializtion Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | ppc: Clean up calling of misc_init_r() during initPeter Tyser2009-09-22-2/+15
| | | | | | | | | | | | | | | | Remove board-specific #ifdefs for calling misc_init_r() during initializtion Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Heiko Schocher <hs@denx.de>
* | Remove deprecated 'autoscr' command/variablesPeter Tyser2009-09-22-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The more standard 'source' command provides identical functionality to the autoscr command. Environment variable names/values on the MVBC_P, MVBML7, kmeter1, mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. The 'autoscript' and 'autoscript_uname' environment variables are also removed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Heiko Schocher <hs@denx.de>
* | FDT: remove obsolete OF_CPU and OF_SOC macros.Marcel Ziswiler2009-09-22-11/+0
|/ | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-17-1/+2
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| * ppc4xx: Enable commands for FDT enabled Linux booting on AMCC AcadiaStefan Roese2009-09-17-1/+2
| | | | | | | | | | | | | | | | Acadia still used the "old" arch/ppc bootm commands for booting Linux images without FDT. This patch now enables these fdt-aware boot commands for Acadia as well. Signed-off-by: Stefan Roese <sr@denx.de>
* | Correct ffs/fls regression for PowerPC etcSimon Kagstrom2009-09-17-41/+15
|/ | | | | | | | | | | | | | | Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* NAND boot: change NAND loader's relocate SP to CONFIG paramMingkai Hu2009-09-15-0/+2
| | | | | | | | | | So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Repack tlb_table to save spaceKumar Gala2009-09-15-11/+10
| | | | | | | | We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Introduce low level write_tlb functionKumar Gala2009-09-15-0/+4
| | | | | | | | | Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Enable usb ehci support for p2020ds boardRoy Zang2009-09-15-0/+9
| | | | | Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.Scott Wood2009-09-15-0/+2
| | | | | | | | Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood <scottwood@freescale.com>
* mpc8260: remove Ethernet node fixup to use generic FDT code.Marcel Ziswiler2009-09-15-0/+2
| | | | | | | | Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its configs for the common mpc8260 code to use generic Ethernet fixup. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com> Tested-by: Heiko Schocher <hs@denx.de>
* arm: Define test_and_set_bit and test_and_clear bit for ARMSimon Kagstrom2009-09-15-3/+25
| | | | | | Needed for (e.g.) ubifs support to work. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Define ffs/fls for all architecturesSimon Kagstrom2009-09-15-0/+53
| | | | | | | | UBIFS requires fls(), which is not defined for arm (and some other architectures) and this patch adds it. The implementation is taken from Linux and is generic. ffs() is also defined for those that miss it. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* arm: Make arm bitops endianness-independentSimon Kagstrom2009-09-15-28/+19
| | | | | | | | Bring over the bitop implementations from the Linux include/asm-generic/bitops/non-atomic.h to provide endianness-independence. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Move __set/clear_bit from ubifs.h to bitops.hSimon Kagstrom2009-09-15-0/+43
| | | | | | | | | __set_bit and __clear_bit are defined in ubifs.h as well as in asm/include/bitops.h for some architectures. This patch moves the generic implementation to include/linux/bitops.h and uses that unless it's defined by the architecture. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-09-15-117/+10
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| * microblaze: Enable hush parserMichal Simek2009-09-14-1/+7
| | | | | | | | | | | | With Hush parser is possible to change command line in dtb Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Remove AtmarkTechno Suzaku boardMichal Simek2009-09-14-110/+0
| | | | | | | | | | | | | | Users should use microblaze-generic platform. This platform is longer not supported. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * net: Remove old Xilinx Emac driverMichal Simek2009-09-14-4/+1
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Short size of global data and fix malloc sizeMichal Simek2009-09-14-2/+2
| | | | | | | | | | | | | | If is full malloc area global, data are rewrite because there was bad size of malloc area. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | ppc4xx: Rename compactcenter to intipDirk Eibach2009-09-11-4/+4
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-626/+317
|/ | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* r7780mp: fix typo in Ethernet chip model number comment.Marcel Ziswiler2009-09-10-1/+1
| | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
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