summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeLines
* powerpc/t2081qds: Add T2081 QDS board supportShengzhou Liu2014-02-24-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor. T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* x600: Switch to CONFIG_PHYLIBTom Rini2014-02-07-2/+1
| | | | | | | | Now that the designware ethernet driver uses phylib we need to turn it on here. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* net/designware - switch driver to phylib usageAlexey Brodkin2014-02-07-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: add AXS101 board supportAlexey Brodkin2014-02-07-0/+181
| | | | | | | | | | | | | | | | | AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: add Arcangel4 board supportAlexey Brodkin2014-02-07-0/+183
| | | | | | | | | | | | | | | | Arcangel4 is a FPGA-based development board that is used for prototyping and verificationof of both ARC hardware (CPUs) and software running upon CPU. This board avaialble in 2 flavours: * Little-endian (arcangel4) * Big-endian (arcangel4-be) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* arc: bdinfo, image and arc-specific init functions declarations supportAlexey Brodkin2014-02-07-0/+4
| | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* include/usb/s3c_udc.h: Add <asm/sizes.h>Tom Rini2014-02-06-0/+1
| | | | | | | With e0059ea switching to using SZ_1K, we need to #include <asm/sizes.h> here for everyone to build still. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-06-0/+5
|\
| * fpga: zynqpl: Add support for zc7015 deviceMichal Simek2014-02-06-0/+5
| | | | | | | | | | | | Just extend tables with this new device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | usb: mv_udc: Rename to ci_udcMarek Vasut2014-02-06-6/+6
| | | | | | | | | | | | | | | | | | | | The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
* | usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driverLukasz Majewski2014-02-06-4/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* config: Fix line lengths in include/config_distro_defaults.hTom Rini2014-02-05-2/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* config: add config_distro_defaults.hDennis Gilmore2014-02-04-0/+55
| | | | | | | | describe a set of default features that distros can rely on being available. having this common definition means that distros can easily support systems implementing them. Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-1/+62
|\
| * microblaze: Add SPL supportMichal Simek2014-02-04-0/+60
| | | | | | | | | | | | | | Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Enable buffer write for NOR flashesMichal Simek2014-02-04-1/+2
| | | | | | | | | | | | It speeds up writing a lot. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'clk' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+7
|\ \
| * | common: Add new clk commandMichal Simek2014-02-04-0/+7
| |/ | | | | | | | | | | | | | | Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha2014-02-03-13/+29
| | | | | | | | | | | | | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | kmp204x: enable support for SPANSION SPI NORValentin Longchamp2014-02-03-0/+1
| | | | | | | | | | | | | | | | The new prototype and the final series was moved from Micron to Spansion to have a better reset sequence that is easier to support. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | KM: add the KM_UBI_PART_BOOT_OPTS #defineValentin Longchamp2014-02-03-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define can be used if the ubi boot partition (defined for all Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs some additionnal boot options. This is the case for the kmp204x boards since u-boot does not support NAND Flash subpage accesses on this platform, an additionnal argument that defines the VID offstet must be given to the kernel. The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this platform. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | kmp204x: add support for the kmcoge4 boardValentin Longchamp2014-02-03-1/+6
| | | | | | | | | | | | | | | | | | | | The kmcoge4 board is the product board derived from the kmlion1 prototype. The main difference between the 2 boards is that the kmcoge4 does not configure the Local Bus controller for LCS2. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: Minor change to boards.cfg to keep targets in order] Signed-off-by: York Sun <yorksun@freescale.com>
* | kmp204x: I2C deblocking supportRainer Boschung2014-02-03-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for using some GPIOs that are connected to the I2C bus to force the bus lines state and perform some bus deblocking sequences. The KM common deblocking algorithm from board/keymile/common/common.c is used. The GPIO lines used for deblocking the I2C bus are some external GPIOs provided by the QRIO CPLD: - SCL = GPIOA_20 - SDA = GPIOA_21 The QRIO GPIOs act in an open-drain-like manner, for 0 the line is driven low and for 1 the GPIO is set as input and the line gets pulled-up. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | kmp204x: support for QRIO1 bootcounterRainer Boschung2014-02-03-2/+4
| | | | | | | | | | | | | | | | | | | | Make use of the QRIO1 32bit register at 0x20 as bootcounter register Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: Minor change to commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/t104xrdb: Update T1042RDB.h in config folderPrabhakar Kushwaha2014-02-03-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb2 node entry to hwconfig default Remove DDR controller interleaving from hwconfig Move SPI related macros out of "#ifdef CONFIG_SPIFLASH" Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Fix commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/t104xrdb: Update T1040RDB.h in config folderPriyanka Jain2014-02-03-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb2 node entry in "hwconfig string" Remove controller interleaving from hwconfig string as T1040 has only one DDR conroller SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH are move outside so that they are defined for all cases as these macros are also used by other u-boot code Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change to commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-3/+2
|/ | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* arm: am43xx: Add USB spl boot supportDan Murphy2014-01-24-6/+40
| | | | | | | Add the USB host boot support for the am43xx evm Add the macros to boot from a usb drive in uBoot Signed-off-by: Dan Murphy <dmurphy@ti.com>
* spl: common: Support for USB MSD FAT image loadingDan Murphy2014-01-24-0/+3
| | | | | | | | Add SPL support to be able to detect a USB Mass Storage device connected to a USB host. Once a USB Mass storage device is detected the SPL will load the u-boot.img from a FAT partition to target address. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* spl: common: Move FAT funcs to a common fileDan Murphy2014-01-24-0/+5
| | | | | | Move the FAT functions to a common location for reuse. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* powerpc: mpc5xxx: remove redundant CONFIG_MPC5xxx definitionMasahiro Yamada2014-01-24-59/+29
| | | | | | | We do not have to define CONFIG_MPC5xxx in board config headers (and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* sandbox: fix the return type of os_free() functionMasahiro Yamada2014-01-24-1/+1
| | | | | | | The function os_free() returns nothing. Its return type should be "void" rather than "void *". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc86xx: move CONFIG_MPC86xx definition to CPU config.mkMasahiro Yamada2014-01-24-4/+0
| | | | | | | Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk because all target boards with mpc86xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mkMasahiro Yamada2014-01-24-40/+0
| | | | | | | Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc824x: remove redundant CONFIG_MPC824X definitionMasahiro Yamada2014-01-24-13/+0
| | | | | | | We do not have to define CONFIG_MPC824X in board config headers because it is defined in arch/powerpc/cpu/mpc824x/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc512x: remove redundant CONFIG_MPC512X definitionMasahiro Yamada2014-01-24-5/+0
| | | | | | | We do not have to define CONFIG_MPC512X in board config headers because it is defined in arch/powerpc/cpu/mpc512x/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc83xx: remove redundant CONFIG_MPC83xx definitionMasahiro Yamada2014-01-24-20/+0
| | | | | | | We do not have to define CONFIG_MPC83xx in board config headers because it is defined in arch/powerpc/cpu/mpc83xx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: ppc4xx: remove redundant CONFIG_4xx definitionMasahiro Yamada2014-01-24-78/+0
| | | | | | | | | | | | We do not have to define CONFIG_4xx in board config headers because it is defined in arch/powerpc/cpu/ppc4xx/config.mk. include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx". I believe it is a typo because "CONFIG_4x" is not used at all in other files. So, I also deleted "CONFIG_4x" in include/configs/JSE.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* include: delete unused header filesMasahiro Yamada2014-01-24-2473/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* avr32: move CONFIG_AVR32 definition to arch/avr32/config.mkMasahiro Yamada2014-01-24-10/+0
| | | | | | | | | Like other architectures, CONFIG_AVR32 can be defined in arch/avr32/config.mk rather than board header files. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Remove obsolete _LINUX_CONFIG_H macroMasahiro Yamada2014-01-24-3/+0
| | | | | | | | | Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* esdhc: Detecting 8 bit width before mmc initializationHaijun.Zhang2014-01-22-0/+3
| | | | | | | | | | The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* esdhc: Workaround for card can't be detected on T4240QDSHaijun.Zhang2014-01-22-0/+5
| | | | | | | | | | | | | | | Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-144/+105
| | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBIPrabhakar Kushwaha2014-01-21-17/+22
| | | | | | | | | Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. Also add their details in README. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPLPo Liu2014-01-21-4/+126
| | | | | | | | | | | | Using the TPL/SPL method to booting from 8k page NAND flash. - Add 256kB size SRAM tlb for second step booting; - Add spl.c for TPL image boot; - Add spl_minimal.c for minimal SPL image; - Add C29XPCIE_NAND configure; - Modify C29XPCIE.h for nand config and enviroment; Signed-off-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1040qds: Update DDR initialization related settingsPriyanka Jain2014-01-21-3/+3
| | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040QDS -Correct number of chip selects to two as t1040qds supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably read at 400KHz. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and 1600MT/s. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* omap3_beagle: use omap3-beagle.dtb for the C4 revisionRobert Nelson2014-01-17-0/+2
| | | | | | findftd is currently setting fdtfile to undefined for the beagle c4, select omap3-beagle.dtb instead Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
* vexpress/armv8: Fix incorrect ethernet controllerBhupesh Sharma2014-01-17-3/+3
| | | | | | | | | | | | | | This patch enables ethernet support in ARMv8 foundation model. The ARMv8 foundation model supports a SMSC91C111 integrated MAC and PHY module which is present at base address 0x01A000000. The previous implementation had enabled SMSC9115 ethernet controller which is not present on the ARMv8 foundation model. Tested on ARMv8 foundation model v1 and v2 by running ping/tftp between the foundation model and the host PC via a bridged network. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
generated by cgit v1.1 at 2024-12-22 11:39:23 +0000