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* env: Refactor apply into change_okJoe Hershberger2012-12-13-8/+12
| | | | | | | | | | | | | | | | Move the read of the old value to inside the check function. In some cases it can be avoided all together and at the least the code is only called from one place. Also name the function and the callback to more clearly describe what it does. Pass the ENTRY instead of just the name for direct access to the whole data structure. Pass an enum to the callback that specifies the operation being approved. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* env: Refactor do_apply to a flagJoe Hershberger2012-12-13-7/+8
| | | | | | | | | | Use a flag in hsearch_r for insert mode passed from import to allow the behavior be different based on use. Now that "do_check" is called for all imports, ensure console init is complete before updating the console on relocation import Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* Make linux kernel string funcs available to toolsJoe Hershberger2012-12-13-4/+9
| | | | | | | | | | isspace() and strim() are not in the typical user-mode string.h, so put them in a separate compilation unit so that they can be built into tools that need them independent of the other common string functions. This allows code shared by u-boot and the linux user-mode tools to link. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* gpt: Enable support for GPT partition table restoration at Samsung's TratsLukasz Majewski2012-12-13-1/+27
| | | | | | | | | Enable support for GPT partition table restoration at Samsung's Trats development board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
* gpt: Support for GPT (GUID Partition Table) restorationLukasz Majewski2012-12-13-0/+52
| | | | | | | | | The restoration of GPT table (both primary and secondary) is now possible. Function 'gpt_restore' presents example of partition restoration process. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* gpt: The leXX_to_int() calls replaced with ones defined at <compiler.h>Chang Hyun Park2012-12-13-43/+46
| | | | | | | | | | | | Custom definitions of le_XX_to_int functions have been replaced with standard ones, defined at <compiler.h> Replacement of several GPT related structures members with ones indicating its endianness and proper size. Signed-off-by: Chang Hyun Park <heartinpiece@outlook.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* part:efi: Move part_efi.h file to ./includeLukasz Majewski2012-12-13-0/+144
| | | | | | | | | | This move is necessary to export gpt header and GPT partition entries to be used with other commands or subsystems. Additionally the part_efi.h file has been cleaned-up to supress checkpatch's warnings. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* vsprintf:fix: Change type returned by ustrtoulLukasz Majewski2012-12-13-1/+1
| | | | | | | | | | | The ustrtoul shall convert string defined size (e.g. 1GiB) to unsigned long type (as its name implies). Up till now it had returned int, which might cause problems with large numbers (GiB range), when interpreted as U2 signed numbers. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* exynos: Enable hashing functions and EDID for smdk5250Simon Glass2012-12-11-0/+7
| | | | | | | Enable SHA1/SHA256 hashing and the hash command. Also enable EDID support for reading from an LCD. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add console command to access io space registersVadim Bendebury2012-12-11-4/+5
| | | | | | | | | | | | | | | | | | | Provide u-boot console functions to access IO space registers. A no thrills implementation, accessing one register at a time. For example: boot > iod 80 0080: 00000094 boot > iod.w 80 0080: 0094 boot > iod.b 80 0080: 94 boot > iow.b 0x80 12 boot > iod 0x80 0080: 00000012 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* edid: Library of EDID decode and printTom Wai-Hong Tam2012-12-11-0/+275
| | | | | | | | | | | | | | | | | | | This implements a library for accessing EDID data from an LCD panel. This is used to obtain information about the panel such as its resolution and type. This is a tidied-up version of the original code pulled from https://github.com/ynezz/u-boot-edid. The changes we made are: - removed bit fields in the struct; - removed endianness cases in the struct; - fixed some wrong definitions; - fixed to fit 80 columns; - fixed some code styles. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Add hash command to perform hashing using various algorithmsSimon Glass2012-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | This new command supports hashing SHA1 and SHA256. It could be extended to others such as MD5 and the CRC algorithms. The syntax is modeled on those: hash <algorithm> <address> <length> [*<dest_addr> | <dest_envvar>] to calculate a hash, and: hash -v <algorithm> <address> <length> [*<verify_addr> | <verify_envvar>] to verify a hash. Use CONFIG_CMD_HASH to enable the command, CONFIG_SHA1 to enable SHA1 and CONFIG_SHA256 to enable SHA256. The existing sha1sum command remains. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add generic hash APISimon Glass2012-12-11-0/+69
| | | | | | | | We have a SHA1 command and want to add a SHA256 command also. Instead of duplicating the code, create a generic hash API which can process commands for different algorithms. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add strcasecmp() and strncasecmp()Simon Glass2012-12-11-2/+5
| | | | | | | | | | | strncasecmp() is present as strnicmp() but disabled. Make it available and define strcasecmp() also. There is a only a small performance penalty to having strcasecmp() call strncasecmp(), so do this instead of a standalone function, to save code space. Update the prototype in arch-specific headers as needed to avoid warnings. Signed-off-by: Simon Glass <sjg@chromium.org>
* sha256: Use const where possible and add watchdog functionSimon Glass2012-12-11-1/+7
| | | | | | | | | In preparation for making the hash function common, we may as well use const where we can. Also add a watchdog version of the hashing function. Signed-off-by: Simon Glass <sjg@chromium.org>
* sha1: Use const where possible, and unsigned for input lenSimon Glass2012-12-11-17/+9
| | | | | | | | In preparation for making the hash function common, we may as well use const where we can. Also the input length cannot be negative, but may be very large, so use unsigned. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add a command to read raw blocks from a partitionKenneth Waters2012-12-11-0/+1
| | | | | | | | | | Sometimes data is on a block device and within a partition, but not in a particular filesystem. This commands permits reading raw data from a partition. Signed-off-by: Kenneth Waters <kwaters@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Add gettime commandAnton Staaf2012-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Gettime returns the current timer value. If CONFIG_SYS_HZ is defined then the timer value is also converted to seconds. Tegra20 (SeaBoard) # gettime Timer val: 7754 Seconds : 7 Remainder : 754 sys_hz = 1000 There has been some discussion about whether this is useful enough to be included in U-Boot. The following boards do not have CONFIG_SYS_HZ defined: M52277EVB M52277EVB_stmicro M53017EVB M54418TWR M54418TWR_nand_mii M54418TWR_nand_rmii M54418TWR_nand_rmii_lowfreq M54418TWR_serial_mii M54418TWR_serial_rmii Signed-off-by: Anton Staaf <robotboy@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: remove duplicate function signatureNikita Kiryanov2012-12-11-13/+4
| | | | | | | gpio_request() appears twice in asm-generic/gpio.h Remove one of the definitions. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-07-17/+175
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| * x86: Fix coreboot config to boot on ChromebookSimon Glass2012-12-06-14/+12
| | | | | | | | | | | | | | | | | | | | The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Turn on support for EFI's GPT in the coreboot configGabe Black2012-12-06-0/+3
| | | | | | | | | | | | | | This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Enable video displaySimon Glass2012-12-06-2/+8
| | | | | | | | | | | | Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-06-1/+1
| | | | | | | | | | | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * Introduce arch_phys_memset which works like memset but on physical memoryGabe Black2012-12-06-0/+21
| | | | | | | | | | | | | | | | | | | | The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass2012-12-06-0/+3
| | | | | | | | | | | | Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable ICH6 GPIO controller for corebootSimon Glass2012-12-06-0/+4
| | | | | | | | | | | | Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+123
| | | | | | | | | | | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Change e-mail address of Luka PerkovLuka Perkov2012-12-07-2/+2
| | | | | | | | | | | | | | Change e-mail address of Luka Perkov. Signed-off-by: Luka Perkov <luka@openwrt.org> CC: Luka Perkov <uboot@lukaperkov.net>
* | cbfs: Add docbook templateSimon Glass2012-12-06-33/+36
| | | | | | | | | | | | This adds a docbook template for fs, and makes CBFS use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | cbfs: Remove mention of CREDITS filesSimon Glass2012-12-06-3/+0
|/ | | | | | | As requested by Wolfgang, remove references to CREDITS in the CBFS files. Signed-off-by: Simon Glass <sjg@chromium.org>
* 4xx: Fix PCI memory mapping on CPCI405 boardsMatthias Fuchs2012-12-06-4/+4
| | | | | | | | This patch fixes an issue with overlapping PCI regions on boards with more than 64MB RAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc5200: Add a3m071 board supportStefan Roese2012-12-05-0/+380
| | | | | | | This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-03-0/+16
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| * x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass2012-11-30-0/+1
| | | | | | | | | | | | This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Select stdio devices for corebootSimon Glass2012-11-30-0/+12
| | | | | | | | | | | | | | We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add CBMEM console driver for corebootVadim Bendebury2012-11-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds upon the recently introduced CBMEM console feature of coreboot. CBMEM console uses a memry area allocated by coreboot to store the console output. The memory area has a certain structure, which allows to determine where the buffer is, the buffer size and the location of the pointer in the buffer. This allows different phases of the firmware (rom based coreboot, ram based coreboot, u-boot after relocation with this change) to keep adding text to the same buffer. Note that this patch introduces a new console driver and adds the driver to the list of drivers to be used for console output, i.e. it engages only after u-boot relocates. Usiong CBMEM console for capturing the pre-relocation console output will be done under a separate change. >From Linux, run the cbmem.py utility (which is a part of the coreboot package) to see the output, e.g.: vvvvvvvvvvvvvvvvv SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode flags: 64bit ilck stag led pmp pio ... Magic signature found Kernel command line: "cros_secure quiet loglevel=1 console=tty2... ^^^^^^^^^^^^^^^^^ Note that the entire u-boot output fits into the buffer only if the coreboot log level is reduced from the most verbose. Ether the buffer size will have to be increased, or the coreboot verbosity permanently reduced. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | include/linux/byteorder: Always defines __fswab64, __swab64p and __swab64sNobuhiro Iwamatsu2012-11-30-2/+0
|/ | | | | | | | | | | | | | | | | | When __BYTEORDER_HAS_U64__ is not defined, we got warning following: ----- /tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’: /tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’ [-Wimplicit-function-declaration] ----- Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary. This removes __BYTEORDER_HAS_U64__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-x86Tom Rini2012-11-28-10/+7
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| * x86: coreboot: Enable LPC TPMSimon Glass2012-11-28-0/+4
| | | | | | | | | | | | Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Remove coreboot start16 codeSimon Glass2012-11-28-1/+1
| | | | | | | | | | | | | | Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Put global data on the stackGraeme Russ2012-11-28-9/+2
| | | | | | | | | | | | | | | | | | | | Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2012-11-28-8/+60
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| * powerpc/corenet_ds: move SATA config to board configurationZang Roy-R619112012-11-27-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/P2041RDB: Fix Flash address LAW addressYork Sun2012-11-27-4/+10
| | | | | | | | | | | | | | | | | | P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-0/+40
| | | | | | | | | | | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/qoriq: Move FMAN microcode locationYork Sun2012-11-27-3/+3
| | | | | | | | | | | | | | | | | | Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: tegra: use bounce buffer APIsStephen Warren2012-11-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | common: rework bouncebuf implementationStephen Warren2012-11-27-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current bouncebuf API requires all parameters to be passed to both bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf start function to accept a state structure as a parameter, and only require that state struct to be passed to the stop function. This simplifies usage of the bounce buffer by clients. Don't modify the data pointer, but rather store the temporary buffer in this state struct. The bouncebuf code ensures that client code can always use a single buffer pointer in the state structure, irrespective of whether a bounce buffer actually had to be allocated. Move cache management logic into the bounce buffer code, so that each client doesn't have to duplicate this. I believe there's no need to invalidate the buffer before a DMA operation, since flushing the cache should prevent any write-backs. Update the MXS MMC driver for this change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | bouncebuf: remove dummy implementationStephen Warren2012-11-27-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | If any driver ever needs to use the bounce buffer API, it always needs to use it. As such, providing a dummy implementation of those APIs when CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-12-22 06:31:21 +0000