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* tegra: put eMMC environment into the boot sectorsStephen Warren2012-09-07-4/+8
| | | | | | | | | | | | | | | | | When I set up Tegra's config files to put the environment into eMMC, I assumed that CONFIG_ENV_OFFSET was a linearized address relative to the start of the eMMC device, and spanning HW partitions boot0, boot1, general* and the user area in order. However, it turns out that the offset is actually relative to the beginning of the user area. Hence, the environment block ended up in a different location to expected and documented. Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire eMMC. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: detect boot sectors using EXT_CSD_BOOT_MULT tooStephen Warren2012-09-07-0/+1
| | | | | | | | | | | | | | | | | Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set. Note that the Linux kernel enables access to boot partitions solely based on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only influences access to "general" partitions. eMMC devices affected by this issue exist on various NVIDIA Tegra platforms (and presumably many others too), such as Harmony (plug-in eMMC), Seaboard, Springbank, and Whistler (plug-in eMMC). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Enable NAND on TECThierry Reding2012-09-07-2/+10
| | | | | | | | | This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: enable NAND on HarmonyStephen Warren2012-09-07-2/+9
| | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Enable NAND on SeaboardSimon Glass2012-09-07-0/+11
| | | | | | | This enables NAND support for the Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1
| | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* nand: Try to align the default buffersSimon Glass2012-09-07-3/+4
| | | | | | | | | | The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* Merge remote-tracking branch 'u-boot-ti/master' into mAlbert ARIBAUD2012-09-05-0/+83
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| * OMAP3: mt_ventoux: added video supportStefano Babic2012-09-04-0/+16
| | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * OMAP3: mt_ventoux: activate GPIO4Stefano Babic2012-09-04-0/+1
| | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * OMAP3: tam3517: add function to read MAC from EEPROMStefano Babic2012-09-04-0/+66
| | | | | | | | | | | | | | | | The manufacturer delivers the TAM3517 SOM with 4 MAC address. They are stored on the EEPROM of the SOM. The patch adds a function to get their values and set the ethaddr variables. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Merge remote-tracking branch 'u-boot-atmel/master' into mAlbert ARIBAUD2012-09-04-1/+7
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| * Fixes the crippled console output on PortuxG20.Markus Hubig2012-09-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use the serial interface on the PortuxG20 we need to enable the level converter first by setting the PC9 pin to high. The level converter needs some time to settle so we have to use the mdelay() function to wait for some time. Unfortunately we have no timers available at board_early_init_f() so we enable the serial output early within board_postclk_init(). Now the U-Boot output looks fine: | U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32) | | CPU: AT91SAM9G20 | Crystal frequency: 18.432 MHz | CPU clock : 396.288 MHz | Master clock : 132.096 MHz | DRAM: 64 MiB | WARNING: Caches not enabled | NAND: 128 MiB | In: serial | Out: serial | Err: serial | Net: macb0 | Hit any key to stop autoboot: 0 Signed-off-by: Markus Hubig <mhubig@imko.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel: eb_cpux9k2: add ram target configurationJens Scharsig2012-09-04-1/+6
| | | | | | | | | | | | | | | | * add ram target for EB+CPUx9k2 board (eb_cpux9k2_ram_config) Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | integrator: break out common configLinus Walleij2012-09-04-156/+111
|/ | | | | | | | The configuration that is common for all Integrator boards may just as well be stored in a common include file as per pattern from other boards. This eases maintenance quite a bit. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* arm/km: remove unused codeHolger Brunck2012-09-03-1/+0
| | | | | | | | | | | | For some reasons we had an own implementaion of dram_init and dram_init_banksize. This is not needed anymore, use the standard kirkwood functions instead. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* arm/km: fix frequency of the SPI NOR FlashValentin Longchamp2012-09-03-1/+1
| | | | | | | | | According to our last HW measures, this could be raised while still compatible with the potential delays on the lines. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* km/arm: set SPI NOR Flash default parametersValentin Longchamp2012-09-03-0/+4
| | | | | | | | | | | | | These parameters are used by the the sf probe command that are used by our update script and they therefore need to be set for all of our boards. The timing is the same as for the ENV SPI NOR Flash (since it's the same physical device) and takes the boco2 delay on the bus into account. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
* edminiv2: orion5x: fix GPIO inits and valuesAlbert ARIBAUD2012-09-03-4/+9
| | | | | | | | | Orion5x did not actually write GPIO output values or input polarities, and ED Mini V2 had bad or missing values for GPIO settings. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* at91: 9x5: Enable PMECC for 5series ek board.Wu, Josh2012-09-01-0/+7
| | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91: atmel_nand: extract HWECC initialization code into one function: ↵Wu, Josh2012-09-01-1/+1
| | | | | | | | | | | | atmel_hw_nand_init_param(). This patch 1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support. 2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix empty newline at EOF error and move return value check into ifdef] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel: at91sam9x5: add spi flash boot supportBo Shen2012-09-01-4/+16
| | | | | | | | | | | | | Add at91sam9x5 series spi flash boot support Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321 serial flash SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on atmel_spi patch, or else, it will occur receive overrun Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: sam9g10/sam9m10g45: remove CONFIG_ARCH_CPU_INITBo Shen2012-09-01-3/+0
| | | | | | | | Remove CONFIG_ARCH_CPU_INIT for at91sam9g10ek and at91sam9m10g45ek Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on TOT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91sam9263ek: fix 'update' scriptAndreas Bießmann2012-09-01-1/+1
| | | | | | | | The old update script uses 'load_addr' which is never set. Use 'fileaddr' instead which is automagically set by e.g. dhcp. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> cc: Stelian Pop <stelian@popies.net>
* ARM : at91sam9x5 : Remove CONFIG_ARCH_CPU_INITBo Shen2012-09-01-2/+0
| | | | | | | Remove CONFIG_ARCH_CPU_INIT, no need it anymore Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* fsl_esdhc: Remove cache snooping for i.MXBenoît Thébaudeau2012-09-01-1/+0
| | | | | | | | | | | | | | | The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
* efikamx: move and rename Efika MX directories and config files to prepare ↵Matt Sealey2012-09-01-0/+0
| | | | | | | | | | | for new boards * Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory * Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: m28evk: Enable SPI DMAMarek Vasut2012-09-01-0/+1
| | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* MX28: m28evk: Align SSP clock speedMarek Vasut2012-09-01-2/+2
| | | | | | | | | | Align the SSP clock speed with oscilator to achieve higher transfer stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* imx27lite: update with gpio api change (v4)trem2012-09-01-0/+5
| | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* MX: Set a common gpio.h for all i.MXStefano Babic2012-09-01-1/+2
| | | | | | | | | Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
* mx28evk: Remove unneeded 'undef'Fabio Estevam2012-09-01-1/+0
| | | | | | | | There is no need to undef an option that is not enabled by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Move "regs-base.h" include after SoC type configurationOtavio Salvador2012-09-01-8/+9
| | | | | | | | | | | | | | | For i.MX233 addition the base registers need to be change so the SoC definition needs to be known before the header include. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* mx53evk: add boot_mode supportTroy Kisky2012-09-01-0/+3
| | | | | | | This allows a watchdog reset to start the ROM's usb/serial downloader, or boot from an sdcard. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6qsabrelite: add boot_mode supportTroy Kisky2012-09-01-0/+3
| | | | | | | This allows a watchdog reset to start the ROM's usb downloader, or boot from an sdcard. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* apx4devkit: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> include/configs/apx4devkit.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
* m28evk: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm:cache:trats: Enable PL310 L2 Cache Controller at TRATS Samsung boardŁukasz Majewski2012-09-01-2/+4
| | | | | | | | Enable the PL310 L2 cache controller at TRATS Samsung board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: add dp_enabled variable in vidinfo structureDonghwa Lee2012-09-01-0/+1
| | | | | | | | | To support display port in exynos fb driver, added dp_enabled variable in vidinfo structure that set in board file. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm:trats: loaduimage environment variable defied for TRATS targetŁukasz Majewski2012-09-01-0/+1
| | | | | | Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-1/+1
| | | | | | | This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: Add smdk5250-uboot-spl.ldsRajeshwari Shinde2012-09-01-0/+5
| | | | | | | | | | | | | Default spl/u-boot-spl.lds created by spl/Makefile resolves the spl text load addr to 0x0. As 0x0 belongs to iROM addr so Global variables can not be used. Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables in spl. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: Remove unused stack and irq config definesRob Herring2012-09-01-888/+2
| | | | | | | | | | | CONFIG_STACKSIZE is not referenced anywhere except on AVR32, but present in most ARM board config files. IRQs are only enabled for 1 config, so remove the unused config options for IRQ and FIQ stack size as well. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* tegra20: enable SPL for tegra20 boardsAllen Martin2012-09-01-5/+82
| | | | | | | | | | | Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: tec: add tegra20-common-post.hAllen Martin2012-09-01-0/+2
| | | | | | | | | | Add tegra20-common-post.h to be consistent with other tegra20 boards. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: rename CONFIG_MACH_TEGRA_GENERICAllen Martin2012-09-01-1/+1
| | | | | | | | | | | | | | Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA. The meaning of the config options is now: CONFIG_TEGRA - Any tegra chip CONFIG_TEGRA20 - A tegra20 family chip CONFIG_TEGRA30 - A tegra30 family chip (not added yet) Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-81/+81
| | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add Raspberry Pi model B board, using BCM2835 SoCStephen Warren2012-09-01-0/+104
| | | | | | | | | | | | | | | The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM, contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors. For more details, see http://www.raspberrypi.org/. Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack relocation to top of RAM) extracted from work by: Oleksandr Tymoshenko <gonzo@bluezbox.com>. GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Tom Rini <trini@ti.com>
* u8500: Separating mmc config parameters from driverJohn Rigby2012-09-01-0/+8
| | | | | | | | | | Configuration in vexpress and u8500.v1 is different from what is needed in u8500.v2. As such, card configuration specifics need to reside in the board file rather than the driver. Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* snowball: applying power to LAN and GBF controllersMathieu J. Poirier2012-09-01-0/+1
| | | | | | | | LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>