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* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-40/+0
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* fdt: Added helper to set PCI dma-ranges propertyKumar Gala2008-10-24-0/+5
| | | | | | | | | | | Added fdt_pci_dma_ranges() that parses the pci_region info from the struct pci_controller and populates the dma-ranges based on it. The max # of windws/dma-ranges we support is 3 since on embedded PowerPC based systems this is the max number of windows. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* fdt: Add fdt_getprop_u32_default helpersKumar Gala2008-10-24-0/+2
| | | | | | | | | Add helper functions to return find a node and return it's property or a default value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* 86xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+2
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* 85xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+9
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-16/+24
| | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* 85xx: remove unused config definitionDave Liu2008-10-24-18/+0
| | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+2
| | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov2008-10-21-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add TSECs' HRCWH masks for MPC837x processorsAnton Vorontsov2008-10-21-0/+2
| | | | | | | We'll use these masks to parse TSEC modes out of HRCWH. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: serdes: add forgotten shifts for rfcksAnton Vorontsov2008-10-21-5/+5
| | | | | | | | | | The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-14/+11
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* FDT: don't use private kernel header filesWolfgang Denk2008-10-21-14/+25
| | | | | | | | | | | | | | On some systems (for example Fedora Core 4) U-Boot builds with the following wanrings only: ... In file included from /home/wd/git/u-boot/include/libfdt_env.h:33, from fdt.c:51: /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead! This patch fixes this problem. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-293/+781
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| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-0/+31
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+231
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Update configs for Netstal boardsNiklaus Giger2008-10-21-275/+292
| | | | | | | | | | | | | | | | | | | | I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-18/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | TQM8260: environment in flash instead EEPROM, baudrate 115kWolfgang Denk2008-10-21-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | strmhz(): Round numbers when printing clock frequenciesWolfgang Denk2008-10-21-2/+3
| | | | | | | | | | | | | | | | | | Round clock frequencies for printing. Many boards printed off clock frequencies like 399 MHz instead of the exact 400 MHz because numberes were not rounded. This is fixed now. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFGTimur Tabi2008-10-21-0/+1
| | | | | | | | | | | | | | | | | | Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. The changelog for that commit is also wrong, as it says "bit 28" when it should be "bit 24". Signed-off-by: Timur Tabi <timur@freescale.com>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-36925/+37419
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Merge 'next' branchWolfgang Denk2008-10-18-36787/+37274
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * mgcoge: add redundant environment sectorHeiko Schocher2008-10-18-0/+5
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgsuvd: update size of environmentHeiko Schocher2008-10-18-3/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+3
| | | | | | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | * Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+24
| | | | | | | | | | | | | | | | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * 85xx: Enable interrupt and setexpr commands on Freescale 85xx boardsKumar Gala2008-10-18-0/+18
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * mgsuvd: fix compiler warning when using soft_i2c driverHeiko Schocher2008-10-18-9/+9
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgsuvd: fix coding styleHeiko Schocher2008-10-18-6/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge: added CONFIG_FIT to support the new u-boot image formatHeiko Schocher2008-10-18-0/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-36823/+36823
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| | * Expose command table search for sub-commandsKumar Gala2008-10-18-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sub-command can benefit from using the same table and search functions that top level commands have. Expose this functionality by refactoring find_cmd() and introducing find_cmd_tbl() that sub-command processing can call. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * mgsuvd, mgcoge: added BOOTCOUNT feature.Heiko Schocher2008-10-18-0/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: added support for the IVM EEprom.Heiko Schocher2008-10-18-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * hush: add showvar command for hush shell.Heiko Schocher2008-10-18-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new command shows the local variables defined in the hush shell: => help showvar showvar - print values of all hushshell variables showvar name ... - print value of hushshell variable 'name' Also make the set_local_var() and unset_local_var () no longer static, so it is possible to define local hush shell variables at boot time. If CONFIG_HUSH_INIT_VAR is defined, u-boot calls hush_init_var (), where boardspecific code can define local hush shell variables at boottime. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * I2C: adding new "i2c bus" Command to the I2C Subsystem.Heiko Schocher2008-10-18-0/+25
| | | | | | | | | | | | | | | | | | | | | With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add board specific I2C deblocking mechanism.Heiko Schocher2008-10-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add DTT (LM75) support.Heiko Schocher2008-10-18-0/+18
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: added EEprom support.Heiko Schocher2008-10-18-0/+15
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add I2C support.Heiko Schocher2008-10-18-0/+68
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-12-23 22:50:25 +0000