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* ARM: tegra: make use of negative ENV_OFFSET on NVIDIA boardsStephen Warren2013-06-13-8/+8
| | | | | | | | | | | Use a negative value of CONFIG_ENV_OFFSET for all NVIDIA reference boards that store the U-Boot environment in the 2nd eMMC boot partition. This makes U-Boot agnostic to the size of the eMMC boot partition, which can vary depending on which eMMC device was actually stuffed into the board. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: report capacity for the selected partitionStephen Warren2013-06-13-0/+7
| | | | | | | | | | | | | Enhance the MMC core to calculate the size of each MMC partition, and update mmc->capacity whenever a partition is selected. This causes: mmc dev 0 1 ; mmcinfo ... to report the size of the currently selected partition, rather than always reporting the size of the user partition. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: fix env in mmc with redundant compile errorBo Shen2013-06-13-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The commit d196bd8 (env_mmc: add support for redundant environment) introduce the following compile error when enable redundant environment support with MMC ---8<--- env_mmc.c:149: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:267: error: 'env_t' has no member named 'flags' make[1]: *** [env_mmc.o] Error 1 --->8--- Add this patch to fix it Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Michael Heimpold <mhei@heimpold.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-74xx-7xxTom Rini2013-06-11-1/+1
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| * ppc: ppmc7xx: Fix possible out-of-bound accessMarek Vasut2013-06-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flash_info_t->start[] field is limited in size by CONFIG_SYS_MAX_FLASH_SECT macro, which is set to 19 for this board in the board config file. If we inspect the board/ppmc7xx/flash.c closely, especially the flash_get_size() function, we can notice the "switch ((long)flashtest)" at around line 80 having a few results which will set flash_info_t->sector_count to value higher than 19, for example "case AMD_ID_LV640U" will set it to 128. Notice that right underneath, iteration over flash_info_t->start[] happens and the upper bound for the interation is flash_info_t->sector_count. Now if the sector_count is 128 as it is for the AMD_ID_LV640U case, but the CONFIG_SYS_MAX_FLASH_SECT limiting the start[] is only 19, an access past the start[] array much happen. Moreover, during this iteration, the field is written to, so memory corruption is inevitable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Richard Danter <richard.danter@windriver.com>
* | powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7Scott Wood2013-06-11-0/+1
|/ | | | | | | | | | | C99's strict aliasing rules are insane to use in low-level code such as a bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the past, add a union so that 16-bit accesses can be performed. Compile-tested only. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* pci: introduce CONFIG_PCI_INDIRECT_BRIDGE optionGabor Juhos2013-06-07-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* generic_board: reduce the redundancy of gd_t struct membersMasahiro Yamada2013-06-07-3/+0
| | | | | | | | | | | | | | | | | | | | | | This commit refactors common/board_f.c and common/board_r.c in order to delete the dest_addr and dest_addr_sp from gd_t struct. As mentioned as follows in include/asm-generic/global_data.h, /* TODO: is this the same as relocaddr, or something else? */ unsigned long dest_addr; /* Post-relocation address of U-Boot */ dest_addr is the same as relocaddr. Likewise, dest_addr_sp is the same as start_addr_sp. It seemed dest_addr/dest_addr_sp was used only as a scratch variable to calculate relocaddr/start_addr_sp, respectively. With a little refactoring, we can delete dest_addr and dest_addr_sp. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org>
* am335x: enable falcon boot mode for mmc (raw and fat) and nandPeter Korsgaard2013-06-07-3/+27
| | | | | | | | | | | | | | | | Jump into full u-boot mode if a 'c' character is received on the uart. We need to adjust the spl bss/malloc area to not overlap with the loadaddr of the kernel (sdram + 32k), so move it past u-boot instead. For raw mmc, we store the kernel parameter area in the free space after the MBR (if used). For nand, we use the last sector of the partition reserved for u-boot. This also enables the spl command in the full u-boot so the kernel parameter area snapshot can be created. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* devkit8000: Add SPL_OS for MMC supportTom Rini2013-06-07-0/+8
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-06-07-0/+5
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| * ARM: bcm2835: add simplefb DT node during bootz/mStephen Warren2013-06-05-0/+2
| | | | | | | | | | | | | | | | | | | | Add a DT simple-framebuffer node to DT when booting the Linux kernel. This will allow the kernel to inherit the framebuffer configuration from U-Boot, and display a graphical boot console, and even run a full SW- rendered X server. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
| * lcd: add functions to set up simplefb device treeStephen Warren2013-06-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | simple-framebuffer is a new device tree binding that describes a pre- configured frame-buffer memory region and its format. The Linux kernel contains a driver that supports this binding. Implement functions to create a DT node (or fill in an existing node) with parameters that describe the framebuffer format that U-Boot is using. This will be immediately used by the Raspberry Pi board in U-Boot, and likely will be used by the Samsung ARM ChromeBook support soon too. It could well be used by many other boards (e.g. Tegra boards with built-in LCD panels, which aren't yet supported by the Linux kernel). Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
* | am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>Tom Rini2013-06-06-9/+6
| | | | | | | | | | | | | | | | | | | | The location of valid scratch space is dependent on SoC, so move that there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On am33xx/ti814x we want to use what the ROM defines as "public stack" which is the area after our defined download image space. Correct the comment about and location of CONFIG_SPL_TEXT_BASE. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-05-6/+24
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| * | am33xx: Correct NON_SECURE_SRAM_START/ENDTom Rini2013-06-04-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Sricharan's cleanup of the boot parameter saving code, we did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a problem that the address was pointing to the middle of our running SPL. Correct to point to the base location of the download image area. Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being used. As part of correcting these tests, make use of the fact that we've always been placing our stack outside of the download image area (which is fine, once the downloaded image is run, ROM is gone) so correct the max size test to be the ROM defined top of the download area to where we link/load at. Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Fix typo noted by Peter Korsgaard
* | | Merge branch 'tpm' of git://git.denx.de/u-boot-x86Tom Rini2013-06-05-4/+6
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| * | | tpm: Reorganize the I2C TPM driverTom Wai-Hong Tam2013-06-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does a similar code reogranzation from http://patchwork.ozlabs.org/patch/132179/ which is based on an old version of code (fdt support and bus selection still not in). It merges this tidy-up on top of the recent code. It does not make any logical change. tpm.c implements the interface defined in tpm.h based on underlying LPC or I2C TPM driver. tpm.c and the underlying driver communicate throught tpm_private.h. Note: Merging the LPC driver with tpm.c is left to future patches. Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | tpm: Add support for new Infineon I2C TPM (SLB 9645 TT 1.2 I2C)Vincent Palatin2013-06-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs, which supports clockstretching, combined reads and a bus speed of up to 400khz. The device also has a new device id. This is based on the kernel patch provided by Infineon : https://gerrit.chromium.org/gerrit/42332 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
| * | | x86: config: Reflect the name changes of LPC TPM configsTom Wai-Hong Tam2013-06-03-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | bootstage: Remove unused entries related to kernel/ramdisk/fdt loadSimon Glass2013-06-04-26/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the code for loading these three images from a FIT is common, we don't need individual boostage IDs for each of them. Note: there are some minor changes in the bootstage numbering, particuarly for kernel loading. I don't believe this matters. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | image: Use fit_image_load() to load kernelSimon Glass2013-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new common code to load a kernel. The functionality should not change. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | image: Use fit_image_load() to load FDTSimon Glass2013-06-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new common code to load a flat device tree. Also fix up a few casts so that this code works with sandbox. Other than that the functionality should not change. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | image: Use fit_image_load() to load ramdiskSimon Glass2013-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new common code to load a ramdisk. The functionality should not change. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | image: Introduce fit_image_load() to load images from FITsSimon Glass2013-06-04-2/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present code to load an image from a FIT is duplicated in the three places where it is needed (kernel, fdt, ramdisk). The differences between these different code copies is fairly minor. Create a new function in the fit code which can handle any of the requirements of those cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | bootstage: Introduce sub-IDs for use with image loadingSimon Glass2013-06-04-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading a ramdisk, kernel or FDT goes through similar stages. Create a block of IDs for each task, and define a consistent numbering within the block. This will allow use of common code for image loading. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | main: Separate out the two abortboot() functionsSimon Glass2013-06-04-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two implementations of abortboot(). Turn these into two separate functions, and create a single abortboot() which calls either one or the other. Also it seems that nothing uses abortboot() outside main, so make it static. At this point there is no further use of CONFIG_MENU in main.c. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: Add prototype for update_tftpSimon Glass2013-06-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This function should be declared in net.h. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | at91: Correct CONFIG_AUTOBOOT_PROMPT definition for pm9263Simon Glass2013-06-04-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | This is not currently used, since autoboot is not enabled for this board, but the string is missing a parameter. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-05-31-165/+329
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| * | mtd: resync with Linux-3.7.1Sergey Lapin2013-05-31-164/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | nand/fsl_ifc: Convert to self-initPrabhakar Kushwaha2013-05-22-1/+2
| | | | | | | | | | | | | | | | | | Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-1805/+566
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/p5040: enable PBL tool supportShaohui Xie2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | cfi_flash: Fix unaligned accesses to cfi_qry structureAndrew Gabbasov2013-05-23-7/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Packed structure cfi_qry contains unaligned 16- and 32-bits members, accessing which causes problems when cfi_flash driver is compiled with -munaligned-access option: flash initialization hangs, probably due to data error. Since the structure is supposed to replicate the actual data layout in CFI Flash chips, the alignment issue can't be fixed in the structure. So, unaligned fields need using of explicit unaligned access macros. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mmc: update Faraday FTSDC010 for rw performanceKuo-Jung Su2013-05-15-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-16/+33
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| | * | T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc: Add T4160QDSYork Sun2013-05-14-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Move SoC define into boards.cfgYork Sun2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-14-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: fix XAUI card PHY addressShaohui Xie2013-05-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-08-28 02:15:12 +0000