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* armv7/ls1021a/etsec: Enable Tx Data and TxBD snoopingAlison Wang2015-08-03-4/+0
| | | | | | | | | To improve eTSEC performance on LS1021A Rev2.0, snooping of all transmit frames from memory and all transmit BD memory accesses in enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021atwr: added deep sleep support in ubootTang Yuantian2015-08-03-1/+10
| | | | | | Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/lS1021atwr: Enable bootscript for secure bootgaurav rana2015-08-03-0/+1
| | | | | | | | Enable bootscript support in secure boot for establishing chain of trust on LS1021atwr. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021a: Reserve secure code into RAM instead of OCRAMZhuoyu Zhang2015-08-03-2/+0
| | | | | | | | | For ls1021a, Reserve secure code in to memory in case OCRAM is needed by other usage. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-148/+539
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| * imx: mx6ul_14x14_evk add basic board supportPeng Fan2015-08-02-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: imx6_spl add mx6ul supportPeng Fan2015-08-02-1/+1
| | | | | | | | | | | | | | i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use same address with i.MX6SX. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6ULPeng Fan2015-08-02-1/+1
| | | | | | | | | | | | | | DRAM space starts from 0x80000000 for i.MX6UL, so need to fix LOADADDR, SYS_TEXT_BASE. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul remove errata for i.MX6ULPeng Fan2015-08-02-1/+3
| | | | | | | | | | | | | | | | Since i.MX6UL use A7 core, but not A9 core, we do not need the erratas for i.MX6UL. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * sf: kconfig: add kconfig options for spi flashesNikita Kiryanov2015-08-02-8/+0
| | | | | | | | | | | | | | | | | | | | Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig. Cc: Jagan Teki <jteki@openedev.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * usb: kconfig: usb keyboard kconfigNikita Kiryanov2015-08-02-2/+0
| | | | | | | | | | | | | | | | | | | | Add Kconfig options for USB keyboard and use them for cm-fx6. Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * arm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig optionNikita Kiryanov2015-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Add USB_EHCI_MX6 option to menuconfig and use it when migrating cm-fx6 usb config to defconfig. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * arm: mx6: cm-fx6: move CMD configs to defconfigNikita Kiryanov2015-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | Move CONFIG_CMD_* options that can be selected in menuconfig to cm-fx6 defconfig. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * arm: mx6: cm-fx6: make it possible to not init displayNikita Kiryanov2015-08-02-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a cm-fx6 specific board_video_skip() to provide the option to not initialize the display. The new function does not init display if the environment variable "panel" is not defined, or if it is set to an unsupported value. Collateral changes: - Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific). - Don't use detect_hdmi(), since env controlled init makes it unnecessary. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportPeng Fan2015-08-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: mx6sabresd/sabreauto runtime setting fdt_filePeng Fan2015-08-02-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable. Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * cgtqmx6eval: Use standard boot scriptOtavio Salvador2015-07-26-28/+66
| | | | | | | | | | | | | | Use more standard boot scripts and also add the capability of booting via NFS. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Add SATA supportOtavio Salvador2015-07-26-0/+9
| | | | | | | | | | | | Add SATA support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Add splash screen supportOtavio Salvador2015-07-26-0/+20
| | | | | | | | | | | | Add LVDS and HDMI support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Add USB supportOtavio Salvador2015-07-26-0/+15
| | | | | | | | | | | | Add USB support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Add PMIC supportOtavio Salvador2015-07-26-0/+13
| | | | | | | | | | | | | | | | cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Add thermal supportOtavio Salvador2015-07-26-0/+8
| | | | | | | | | | | | | | | | Add thermal support so that we can see the following message on boot: CPU: Industrial temperature grade (-40C to 105C) at 33C Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Use the default CONFIG_SYS_PBSIZEOtavio Salvador2015-07-26-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * cgtqmx6eval: Use default promptOtavio Salvador2015-07-26-3/+0
| | | | | | | | | | | | Remove the custom prompt and use the default instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * warp: Add MAX77696 supportFabio Estevam2015-07-26-0/+11
| | | | | | | | | | | | | | | | Warp has a MAX77696 PMIC connected via I2C1 bus. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-26-0/+60
| | | | | | | | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * thermal: Fix commentsFabio Estevam2015-07-26-12/+4
| | | | | | | | | | | | | | | | | | | | It seems that many comments were copied from the I2C uclass, so adjust the comments for the thermal class. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoMStefan Roese2015-07-26-0/+73
| | | | | | | | | | | | | | | | | | This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-66/+144
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| * | imx6: standardise OCOTP and fuse config to mx6_commonPeter Robinson2015-07-10-68/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to README.mxc_ocotp the OCOTP is a stanard i.MX6 SoC feature so centralise the config in mx6_common.h so functionality is standard across all boards Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-10-2081/+977
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| * | | mx53loco: Use generic 'load' command instead of 'fatload'Guillaume GARDET2015-07-06-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board. This allows to use EXT partition instead of FAT, while keeping FAT compatibility. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Jason Liu <r64343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-07-31-22/+99
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| * | | | powerpc/t1023rdb: add support for T1023RDB RevCShengzhou Liu2015-07-31-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for NOR flash and GPIO/I2C switch control on RevC. - NOR support - bank0/bank4 switch - SD/eMMC switch - board version Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAMAneesh Bansal2015-07-31-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/T102xRDB: Enable ifc nand ecc encode and decodeJaiprakash Singh2015-07-28-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC nand ecc encode and decode mode are not correctly set in CSOR register during nand initialization.Enable ecc encode/decode in 4-bit mode Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/T104xD4RDB: Add T104xD4RDB boards supportPriyanka Jain2015-07-28-10/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-3/+516
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| * | | | | T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+342
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: tegra: Use architected timer on ARMv8Thierry Reding2015-07-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8 requires an architected timer to be present, so it can be used instead of the Tegra US timer. This allows for better code reuse. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: tegra: Disable SPL and non-cached memory on 64-bitThierry Reding2015-07-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in AArch64 mode so that we don't need the SPL. Non-cached memory is not implemented (yet) for 64-bit ARM. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | pxe: add AArch64 image supportStephen Warren2015-07-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sysboot and pxe commands currently support either U-Boot formats or raw zImages. Add support for the AArch64 Linux port's native image format too. As with zImage support, there is no auto-detection of the native image format. Rather, if the image is auto-detected as a U-Boot format, U-Boot will try to interpret it as such. Otherwise, U-Boot will fall back to a raw/native image format, if one is enabled. My belief is that CONFIG_CMD_BOOTZ won't ever be enabled for any AArch64 port, hence there's never a need to differentiate between CONFIG_CMD_ _BOOTI and _BOOTZ at run-time; compile-time will do. Even if this isn't true, we want to prefer _BOOTI over _BOOTZ when defined, since _BOOTI is definitely the native format for AArch64. Change-Id: I83c5cc7566032afd72516de46f4e5eb7a780284a Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | tegra124: Expand SPL space by 8KBSimon Glass2015-07-27-1/+1
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are getting very close to running out of space in SPL, and with the currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | | Fix incorrect comments in linker_lists.hBin Meng2015-07-28-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This corrects several typos in the comment block as well as some indentions and nits in the linker_lists.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-9/+69
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| * | | | | ARM: zynqmp: Wire up SATA for the boardMichal Simek2015-07-28-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SATA for the ZynqMP targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | ARM: zynqmp: Wire up ethernet controllersMichal Simek2015-07-28-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-09-04 00:25:34 +0000