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* ARM: uniphier: move CONFIG_I2C_EEPROM to defconfigMasahiro Yamada2016-07-26-1/+0
| | | | | | | We already have the entry for this option in Kconfig, so let's migrate to it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-25/+70
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| * armv8/ls1043a: Add MTD partition schemeWenbin Song2016-07-26-2/+20
| | | | | | | | | | | | | | | | Add and share the the MTD partition scheme with kernel by default bootargs. And add the "mtdparts" env. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/ls1046a: Cleanup the environment variablesWenbin Song2016-07-26-4/+1
| | | | | | | | | | | | | | | | Cleanup the variables: "kernel_addr","ramdisk_addr", "ramdisk_size","console". Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1021atwr: Add SD secure boot targetSumit Garg2016-07-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-7/+11
| | | | | | | | | | | | | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * include: usb: Rename USB controller base address mappingRajesh Bhagat2016-07-26-13/+9
| | | | | | | | | | | | | | | | Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-0/+16
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| * | defconfig: am335x_boneblack_vboot: enable i2c driver modelMugunthan V N2016-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable i2c driver model for am335x_boneblack_vboot as omap i2c supports driver model. Also enable CONFIG_DM_I2C_COMPAT for legacy drivers of i2c devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ti_armv7_common: i2c: do not define DM_I2C for splMugunthan V N2016-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Since omap's spl doesn't support DM currently, do not define DM_I2C for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM64: rockchip: add support for rk3399 SoC based evbKever Yang2016-07-25-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dts: add support for Rockchip rk3399 socKever Yang2016-07-25-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files are from kernel upstream: "649a371 Add linux-next specific files for 20160616" with some modification need by U-Boot: - chosen with stdout-path to uart2. - add clock-frequency for uart2 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Add a way to find a device by its driverSimon Glass2016-07-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs have a single clock device. Provide a way to find it given its driver name. This is handled by the linker so will fail if the name is not found, avoiding strange errors when names change and do not match. It is also faster than a string comparison. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3288: add fastboot supportXu Ziyuan2016-07-25-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | usb: dwc2-otg: adjust fifo size via platform dataXu Ziyuan2016-07-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The total FIFO size of some SoCs may be different from the existen, this patch supports fifo size setting from platform data. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | usb: rockchip-phy: implement USB2.0 phy controlXu Ziyuan2016-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and Innosilicon. This patch applys dwc2 usb driver framework to implement phy_init() and phy_off() methods for Synopsys phy on Rockchip platform. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: add basic support for evb-rk3288 boardXu Ziyuan2016-07-25-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: add option to change method of loading u-bootXu Ziyuan2016-07-25-0/+5
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Migrate CONFIG_I2C_EEPROMTom Rini2016-07-25-1/+0
| | | | | | | | | | | | | | | | | | Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago, but sandbox was skipped. Leave it off for sandbox_spl where it does not build, but does not need to be either. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-07-25-1/+16
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| * | mtd: fix compiler warningsSteve Rae2016-07-24-0/+5
| | | | | | | | | | | | | | | | | | | | | - add missing declaration - update debug output format specifiers Signed-off-by: Steve Rae <steve.rae@raedomain.com>
| * | sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS valueBoris Brezillon2016-07-24-0/+1
| | | | | | | | | | | | | | | | | | | | | On some sunxi boards we have NANDs exposing 1664 OOB bytes per page. Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | mtd: nand: Increase the max OOB sizeBoris Brezillon2016-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | Some NANDs are now exposing 1664 OOB bytes per page. Adjust the NAND_MAX_OOBSIZE value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * | mtd: nand: add common DT init codeBrian Norris2016-07-24-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are already-documented common bindings for NAND chips. Let's handle them in nand_base. If NAND controller drivers need to act on this data before bringing up the NAND chip (e.g., fill out ECC callback functions, change HW modes, etc.), then they can do so between calling nand_scan_ident() and nand_scan_tail(). The original commit has been slightly reworked to use the fdtdec_xxx() helpers (instead of the of_xxxx() ones). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | sandbox: Add instructions about building on 32-bit machinesSimon Glass2016-07-25-1/+4
|/ | | | | | | | Sandbox is built with 64-bit ints by default. This doesn't work properly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: fix doubled tftpboot commandsMasahiro Yamada2016-07-23-1/+0
| | | | | | This downloads the same file twice for nothing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* gdsys: Drop print_fpga_state functionTom Rini2016-07-22-1/+0
| | | | | | | | | | On most platforms the print_fpga_state function is never called. Only on dlvision-10g do we, so in that case inline it. Drop it from everywhere else to avoid extra strings. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Acked-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* igep00x0: generate default mtdparts according NAND chip usedLadislav Michl2016-07-22-0/+1
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* igep00x0: UBIizeLadislav Michl2016-07-22-47/+38
| | | | | | | | | | | | Convert IGEP board to use UBI volumes for U-Boot, its environment and kernel. With exception of first four sectors read by SoC boot ROM whole (One)NAND is UBI managed. Also merge NAND and OneNAND defconfigs as now one binary can serve both flashes. As code is too big now, drop CONFIG_SPL_EXT_SUPPORT to make it fit. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* mtd: OneNAND: allow board init function failLadislav Michl2016-07-22-1/+1
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: armv7: introduce set_gpmc_cs0Ladislav Michl2016-07-22-0/+1
| | | | | | Allow boards to runtime detect flash type. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-1/+1
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: support loading from UBI volumesLadislav Michl2016-07-22-0/+4
| | | | | | | | Add support for loading from UBI volumes on the top of NAND and OneNAND. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-22-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* onenand_spl_simple: Add a simple OneNAND read functionLadislav Michl2016-07-22-0/+1
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* nand_spl_simple: Add a simple NAND read functionThomas Gleixner2016-07-22-0/+1
| | | | | | | | | | | To support UBI in SPL we need a simple NAND read function. Add one to nand_spl_simple and keep it as simple as it goes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* i2c_eeprom: Add reading supportmario.six@gdsys.cc2016-07-22-0/+4
| | | | | | | | | | | | | | This patch implements the reading functionality for the generic I2C EEPROM driver, which was just a non-functional stub until now. Since the page size will be of importance for the writing support, we add suitable members to the private data structure to keep track of it. Compatibility strings for a range of at24c* chips are added. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-93/+2
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| * zynq: defconfig: Remove unnecessary board specific config filesSiva Durga Prasad Paladugu2016-07-22-60/+0
| | | | | | | | | | | | | | | | | | Remove unnecessary board specifc config files for zynq boards(microzed, picozed, ZC770(all), zed) and point to zynq common config file. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfigSiva Durga Prasad Paladugu2016-07-22-17/+0
| | | | | | | | | | | | | | | | Enable config CONFIG_SYS_NO_FLASH through defconfig for all zynq boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * usb: zynq: Define config USB_STORAGE through defconfigSiva Durga Prasad Paladugu2016-07-22-1/+0
| | | | | | | | | | | | | | | | Define config USB_STORAGE through defconfig for all respective zynq boards Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQSiva Durga Prasad Paladugu2016-07-22-11/+1
| | | | | | | | | | | | | | | | | | Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Enable AHCI on EP platformAlexander Graf2016-07-22-0/+1
| | | | | | | | | | | | | | | | The EP platform also has working AHCI emulation, so I see little reason not to implement the plumbing for it that enables us to boot from AHCI. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Remove empty ifdef around cachesMichal Simek2016-07-22-4/+0
| | | | | | | | | | | | Code around was removed because of move to Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-07-21-44/+87
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| * powerpc/85xx: Increase fdt addressScott Wood2016-07-21-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading the fdt at 0xc00000 fails if the uncompressed kernel image is greater than 12 MiB, which is quite common with modern kernels and multiplatform defconfigs. Move fdtaddr to 0x1e00000 which is just under the ramdiskaddr on most targets. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Paul Gortmaker <paul.gortmaker@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-08-23 04:59:29 +0000