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* Introduce a header file for the BIOS emulatorSimon Glass2014-11-25-0/+43
| | | | | | | We should have a public header so that users can avoid defining functions themselves. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a definition of asmlinkageSimon Glass2014-11-25-0/+3
| | | | | | | This is needed to permit calling C from assembler without too much pain. Add a definition for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable SPI for chromebook_linkSimon Glass2014-11-25-4/+0
| | | | | | Enable SPI so that the SPI flash can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+1
| | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable USB on linkSimon Glass2014-11-25-2/+0
| | | | | | Enable USB support on link - there are two EHCI ports available. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-1/+0
| | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+1
| | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Add functions to read and write a BAR addressSimon Glass2014-11-25-0/+23
| | | | | | | | | Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: config: Enable plug-and-play for link PCISimon Glass2014-11-25-0/+3
| | | | | | | | Enable this option so that we can configure the available PCI devices. Also make sure that PCI is available early after relocation as we use it for several other subsystems. Signed-off-by: Simon Glass <sjg@chromium.org>
* rtc: mc146818: Set up RTC at start of daySimon Glass2014-11-25-0/+5
| | | | | | | Provide a function to set up the RTC ready for use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove board_early_init_r()Simon Glass2014-11-25-1/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Update pci_ids.h to include some missing IDsSimon Glass2014-11-25-6/+181
| | | | | | | This was taken from Linux 3.18 with some additional IDs from Chrome OS Coreboot commit 688ef385. Signed-off-by: Simon Glass <sjg@chromium.org>
* Fix SIZE_MAX compiler warning when using stdint.hSimon Glass2014-11-25-0/+2
| | | | | | | This new symbol may be defined by the compiler. If it is, avoid a compiler warning when USE_STDINT is defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-24-6/+0
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| * ARM: Add arch/arm/cpu/armv7/Kconfig with non-secure and virt optionsHans de Goede2014-11-24-6/+0
| | | | | | | | | | | | | | | | | | Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a preparation patch for adding an env variable to choose between secure / non-secure boot on non-secure boot capable systems, specifically this prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-18/+186
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| * | cmd_sata: implement sata stop commandNikita Kiryanov2014-11-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement sata stop command. This introduces the __sata_stop() weak function, which mirrors the weak __sata_initialize() function, giving users the option of undoing the custom steps performed in overrides of sata_initialize(). Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
| * | sata: implement reset_sata for dwc_ahsataNikita Kiryanov2014-11-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add reset_sata() to the sata driver interface and implement it for dwc_ahsata. This function cleans up after sata_init(), and therefore accepts a device number like sata_init() does. A dummy implementation is provided for the rest of the drivers. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | mx6: mx6sabre common: Enable i.MX thermal DM driverYe.Li2014-11-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable i.MX thermal DM driver to mx6sabre_common.h file. Since the thermal is used in init_sequence_f, so define the CONFIG_SYS_MALLOC_F_LEN to support DM driver using in pre relocation phase. Additional, thermal driver depends on ocotp, make sure to enable CONFIG_MXC_OCOTP when CONFIG_IMX6_THERMAL is selected. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| * | DM: thermal: Add imx thermal DM driverYe.Li2014-11-21-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | Add a new thermal uclass for thermal sensor and implement the imx thermal driver basing on this uclass. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | imx: imx6q/dlsabreauto: Add PMIC Pfuze100 supportYe.Li2014-11-20-0/+6
| | | | | | | | | | | | | | | | | | | | | Add the pfuze100 initialization in power_init_board for imx6q/dl sabreauto board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | power: pfuze100: Update definitions for buck regulatorsYe.Li2014-11-20-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for buck regulators (SW1A/B/C) registers and voltage values. Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * | imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3Ye.Li2014-11-20-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board. The default boot socket is USDHC4, so the MMC environment device and mmcdev variable are set to this device. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | tqma6: (cosmetic) remove CONFIG_FLASH_SECTOR_SIZEMarkus Niebel2014-11-20-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | This is nowhere documented and only used by two other boards. Replace it with TQMA6_SPI_FLASH_SECTOR_SIZE. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | mx6qsabreauto: Add parallel NOR flash supportFabio Estevam2014-11-20-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabreauto boards come with 32 MiB of parallel NOR flash. Add support for it: U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB Flash: 32 MiB NAND: 0 MiB Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is not used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: mx6slevk: Change default mmcdev to USDHC2 deviceYe.Li2014-11-20-1/+1
| | | | | | | | | | | | | | | | | | | | | Since USDHC1 and USDHC3 added, the dev index for USDHC2 changed to 1. So modify the default mmcdev in environment variables to dev 1. Signed-off-by: Ye.Li <B37916@freescale.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-34/+109
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | dm: spi: Use device_bind_driver() instead of our own functionSimon Glass2014-11-22-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI function does the same thing, so we may as well just use the new generic function. The 'cs' parameter was not actually used, so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dm: spi: Correct handling of SPI chip selects in sandboxSimon Glass2014-11-22-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code was not updated when the chip select handling was adjusted. Fix it to call the correct function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dm: Add a function to bind a device by driver nameSimon Glass2014-11-22-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases we need to manually bind a device to a particular driver. Add a function to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dm: core: Add functions to find parent and OF dataSimon Glass2014-11-22-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dev_get_parent() as a convenience to obtain the parent of a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dm: core: Allow access to the device's driver_id dataSimon Glass2014-11-22-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the device is created from a device tree node, it matches a compatible string. Allow access to that string and the associated data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | dm: Disable dm_warn() in SPLSimon Glass2014-11-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since this function can use up quite a bit of space for its strings, disable it by default in SPL. Use CONFIG_DM_WARN to re-enable it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | | dm: Allow stdio registration to be droppedSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a CONFIG_DM_STDIO option to enable registering a serial device with the stdio library. This is seldom useful in SPL, so disable it by default when building for SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | | dm: Allow device removal features to be droppedSimon Glass2014-11-21-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SPL we don't expect to need to remove a device. Save some code space by dropping this feature. The board config can define CONFIG_DM_DEVICE_REMOVE if this is in fact needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | | dm: Split the simple malloc() implementation into its own fileSimon Glass2014-11-21-23/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The simple malloc() implementation is used when memory is tight. It provides a simple buffer with an incrementing pointer. At present the implementation is inside dlmalloc. Move it into its own file so that it is easier to find. Rather than using relocation as a signal that the full malloc() is available, add a special GD_FLG_FULL_MALLOC_INIT flag. This signals that the simple malloc() should no longer be used. In some cases, such as SPL, even the code space used by the full malloc() is wasteful. Add a CONFIG_SYS_MALLOC_SIMPLE option to provide only the simple malloc. In this case the full malloc is not available at all. It saves about 1KB of code space and about 0.5KB of data on Thumb 2. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: tegra: Avoid using arch-specific memcpy() in SPLSimon Glass2014-11-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The faster functions are not actually available in SPL and the code size likely isn't worth it. Use the normal memcpy() in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: at91: Convert snapper9260 to use driver modelSimon Glass2014-11-21-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert this at91sam9260-based board to use driver model. This should serve as an example for other similar boards. Serial and GPIO are supported so far. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | dm: at91: Move snapper9260 to generic baordSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This works correctly, so switch it over before the deadline. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: at91: Correct text base for snapper9260Simon Glass2014-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The value should be 0x21f00000. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-257/+363
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
| * | | | x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: Build a .rom file which can be flashed to an x86 machineSimon Glass2014-11-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet. Create a u-boot.rom output file for this purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: Add chromebook_link boardSimon Glass2014-11-21-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | x86: config: Move common x86 configs to a common fileSimon Glass2014-11-21-256/+260
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many of the x86 CONFIG options will be common across different boards. Move them to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | | dm: gpio: Add a function to read an ID from a list of GPIOsSimon Glass2014-11-21-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For board IDs a common approach is to set aside several GPIOs for use in determining the board ID. This can provide information about board features and the revision. Add a function that turns a list of GPIOs into an integer by assigning each GPIO to a single bit. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: serial: Move current serial port pointer to global_dataSimon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In general we can't store things in the data section until we have inited SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move the pointer to global_data so that it will work on all platforms. Without this fix the serial port will not work prior to relocation with driver model on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 08:23:04 +0000