| Commit message (Collapse) | Author | Age | Lines |
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To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.
This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.
The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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We need to load 'imx6dl-sabresd.dtb' in the mx6dl version.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
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mx6slevk has a SMSC8720 connected in RMII mode.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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In arch/arm/cpu/arm1136/cpu.c we have:
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
,so there is no need to define 'CONFIG_SYS_CACHELINE_SIZE' with the default
size in the board config file.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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The wandboard solo version should boot the 'imx6dl-wandboard.dtb' file, since
dual-lite and solo variants are the same SoC with only the number of cores being
different.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Conflicts:
MAINTAINERS
boards.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Acked-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>
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Add STMP3780-based Sansa Fuze+ board. This board is a small PMP
device sporting a CPU which was later rebranded to i.MX233 .
Currently supported is USB gadget mode and MMC .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
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Add STMP3780-based XFi3 board. This board is a small PMP device
sporting a CPU which was later rebranded to i.MX233 . Currently
supported is USB gadget mode and both external SD and internal
Phison SD-NAND bridge .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
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If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev
and bootpart variables to refer to MMC device 1, it would make sense
that the mmcroot env variable should switch to that device as well.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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dra7xx_evm has eMMC and the default environment can be stored in it.
So enabling saveenv command and the configs to store environment in eMMC.
Tested on DRA752 ES1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework]
Signed-off-by: Tom Rini <trini@ti.com>
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Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Signed-off-by: Tom Rini <trini@ti.com>
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Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM,
AM335x EVM SK and others.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
[trini: Split and rework Avinash's changes into new drivers/power
framework]
Signed-off-by: Tom Rini <trini@ti.com>
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Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte <gguyotte@ti.com>
[trini: Split and rework Greg's changes into new drivers/power
framework]
Signed-off-by: Tom Rini <trini@ti.com>
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Since UBIFS is enabled for cpux9k2, more malloc space is needed.
For the current uboot 2013.10-rcX the size is to small, this will fix the
startup problems by increasing the malloc space to 4MiB.
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Conflicts:
tools/Makefile
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This patch add new functions to pmic max77686 to set voltage and mode.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Arndale board is based on samsung's exynos5250 soc.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Since config.mk is deprecated, remove this file,
and move CONFIG_SYS_TEXT_BASE define to config file.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Since config.mk is deprecated, remove this file,
and move CONFIG_SYS_TEXT_BASE define to config file.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
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Update the Makefiles so that all boards can use the same spl generation tool
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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LCD4 needs a slightly different GPIO configuration than the
original LWMON5 variant. GPIO49 needs to be configured to a
default output value of 0 (permanent voltage supply).
Additionally lcd4 also needs to enable the LSB transmitter.
Signed-off-by: Stefan Roese <sr@denx.de>
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Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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Drop unused CONFIG_NET_MULTI
Signed-off-by: Bo Shen <voice.shen@gmail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Conflicts:
drivers/serial/serial.c
The conflict above was a trivial case of adding one init
function in each branch, and manually resolved in merge.
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Add mkimage support for generating and verifying MXS bootstream.
The implementation here is mostly a glue code between MXSSB v0.4
and mkimage, but the long-term goal is to rectify this and merge
MXSSB with mkimage more tightly. Once this code is properly in
U-Boot, MXSSB shall be deprecated in favor of mkimage-mxsimage
support.
Note that the mxsimage generator needs libcrypto from OpenSSL, I
therefore enabled the libcrypto/libssl unconditionally.
MXSSB: http://git.denx.de/?p=mxssb.git;a=summary
The code is based on research presented at:
http://www.rockbox.org/wiki/SbFileFormat
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
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The target uses AUART 3 instead of the DUART for console output.
Signed-off-by: Andreas Wass <andreas.wass@dalelven.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
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The MMC driver relies on this block now.
Signed-off-by: Tom Rini <trini@ti.com>
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add support for the am335x based boards from siemens:
dxr2:
- DDR3 128MiB
- NAND 256MiB
- Ethernet with external Switch SMSC LAN9303
- no PMIC
- internal Watchdog
- DFU support
pxm2:
- DDR2 512 MiB
- NAND 1024 MiB
- PMIC
- PHY atheros ar803x
- USB Host
- internal Watchdog
- DFU support
rut:
- DDR3 256 MiB
- NAND 256 MiB
- PMIC
- PHY natsemi dp83630
- external Watchdog
- DFU support
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Roger Meier <r.meier@siemens.com>
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Pascal Bach <pascal.bach@siemens.com>
Cc: Tom Rini <trini@ti.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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Re-group the general options to note things that can be removed safely
to reduce binary size when not required, and expand the comment about
what commands we do include to note it could be replaced with a specific
list of required one. While at it, move the CMD parts of various
blocks IP to the end of the list for consistency.
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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While in here, drop CONFIG_BOOTP_DEFAULT as it is unused in the code.
Signed-off-by: Tom Rini <trini@ti.com>
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After examining both TRMs and doing some experimentation, we can rely on
using the start of the download area for CONFIG_SPL_TEXT_BASE and then
move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for
peripheral boot modes such as UART.
Signed-off-by: Tom Rini <trini@ti.com>
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