summaryrefslogtreecommitdiff
path: root/include
Commit message (Collapse)AuthorAgeLines
* keystone: usb: add support of usb xhciWingMan Kwok2014-10-23-1/+22
| | | | | | | | | | | | | Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-0/+1
| | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan2014-10-23-0/+30
| | | | | | | | | | | | | | The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-10-22-76/+566
|\
| * dm: serial: Tidy up the pl01x driverSimon Glass2014-10-22-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the driver so that leaf functions take a pointer to the serial port register base. Put all the global configuration in the init function, and use the same settings from then on. This makes it much easier to move to driver model without duplicating the code, since with driver model we use platform data rather than global settings. The driver is compiled with either the CONFIG_PL010_SERIAL or CONFIG_PL011_SERIAL option and this determines the uart type. With driver model this needs to come in from platform data, so create a new CONFIG_PL01X_SERIAL config which brings in the driver, and adjust the driver to support both peripheral variants. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
| * dm: rpi: Convert GPIO driver to driver modelSimon Glass2014-10-22-0/+5
| | | | | | | | | | | | | | | | | | Convert the BCM2835 GPIO driver to use driver model, and switch over Raspberry Pi to use this, since it is the only board. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * dm: core: Add support for simple-busSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | Add a driver for the simple-bus nodes, which allows devices within these nodes to be bound. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: imx: Move cm_fx6 to use driver model for serial and GPIOSimon Glass2014-10-22-0/+11
| | | | | | | | | | | | | | | | | | Now that serial and GPIO are available for iMX.6, move cm_fx6 over as an example. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| * dm: imx: serial: Support driver model in the MXC serial driverSimon Glass2014-10-22-0/+14
| | | | | | | | | | | | | | Add driver model support with this driver. Boards which use this driver should define platform data in their board files. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Allow a list of devices to be declared in one stepSimon Glass2014-10-22-0/+4
| | | | | | | | | | | | | | The U_BOOT_DEVICE macro allows the declaration of a single U-Boot device. Add an equivalent macro to declare an array of devices, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: linker_lists: Add a way to declare multiple objectsSimon Glass2014-10-22-0/+21
| | | | | | | | | | | | | | | | The existing ll_entry_declare() permits a single element of the list to be added to a linker list. Sometimes we want to add several objects at once. To avoid lots of messy declarations, add a macro to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: cros_ec: Move cros_ec_spi to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | | | Adjust this driver to use driver model and move smdk5420 boards over to use it. Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: sandbox: cros_ec: Move sandbox cros_ec to driver moduleSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | | | Adjust the sandbox cros_ec emulation driver to work with driver model, and switch over to driver model for sandbox cros_ec. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: cros_ec: Add support for driver modelSimon Glass2014-10-22-1/+27
| | | | | | | | | | | | | | | | Add support for driver model if enabled. This involves minimal changes to the code, mostly just plumbing around the edges. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: config: Use driver model for SPI flashSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | Use driver model for exynos5 board SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: sandbox: Convert SPI flash driver to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | Convert sandbox's spi flash emulation driver to use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: Add a uclass for SPI flashSimon Glass2014-10-22-0/+71
| | | | | | | | | | | | | | | | | | | | | | Add a driver model uclass for SPI flash which supports the common operations (read, write, erase). Since we must keep support for the non-dm interface, some modification of the spi_flash header is required. CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Tidy up public and private header filesSimon Glass2014-10-22-52/+5
| | | | | | | | | | | | | | | | Since spi_flash.h is supposed to be the public API for SPI flash, move private things to sf_internal.h. Also tidy up a few comment nits. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * exynos: universal_c210: Move to driver model soft_spiSimon Glass2014-10-22-10/+1
| | | | | | | | | | | | | | Adjust this board to use the driver model soft_spi implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: spi: Remove SPI_INIT featureSimon Glass2014-10-22-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | This feature provides for init of a single SPI port for the soft SPI feature. It is not really compatible with driver model since it assumes a single SPI port. Also, inserting SPI init into the driver by means of a #define is not very nice. This feature is not used by any active boards, so let's remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-2/+1
| | | | | | | | | | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sandbox: Add a SPI emulation uclassSimon Glass2014-10-22-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot includes a SPI emulation driver already but it is not explicit, and is hidden in the SPI flash code. Conceptually with sandbox's SPI implementation we have a layer which creates SPI bus transitions and a layer which interprets them, currently only for SPI flash. The latter is actually an emulation, and it should be possible to add more than one emulation - not just SPI flash. Add a SPI emulation uclass so that other emulations can be plugged in to support different types of emulated devices on difference buses/chip selects. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: spi: Add a uclass for SPISimon Glass2014-10-22-3/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a uclass which provides access to SPI buses and includes operations required by SPI. For a time driver model will need to co-exist with the legacy SPI interface so some parts of the header file are changed depending on which is in use. The exports are adjusted also since some functions are not available with driver model. Boards must define CONFIG_DM_SPI to use driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> (Discussed some follow-up comments which will address in future add-ons)
| * dm: core: Add a clarifying comment on struct udevice's seq memberSimon Glass2014-10-22-1/+2
| | | | | | | | | | | | | | The sequence number is unique within the uclass, so state this clearly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: core: Allow parents to pass data to children during probeSimon Glass2014-10-22-0/+17
| | | | | | | | | | | | | | | | | | | | | | Buses sometimes want to pass data to their children when they are probed. For example, a SPI bus may want to tell the slave device about the chip select it is connected to. Add a new function to permit the parent data to be supplied to the child. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: core: Add functions for iterating through device childrenSimon Glass2014-10-22-0/+18
| | | | | | | | | | | | | | | | Buses need to iterate through their children in some situations. Add a few functions to make this easy. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: exynos: Move serial to driver modelSimon Glass2014-10-22-0/+3
| | | | | | | | | | | | | | Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: gpio: Convert to driver modelSimon Glass2014-10-22-0/+10
| | | | | | | | | | | | | | Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Move s5p_goni to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | | | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for s5p_goni. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Move smdkc100 to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | | | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for smdkc100. Signed-off-by: Simon Glass <sjg@chromium.org>
| * arm: goni: add i2c_init_board()Robert Baldyga2014-10-22-0/+2
| | | | | | | | | | | | | | Add proper initialization of GPIO pins used by software i2c. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: add of_match_ptr() macroMasahiro Yamada2014-10-22-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver model supports two ways for passing device parameters; Device Tree and platform_data (board file). Each driver should generally support both of them because some popular IPs are used on various platforms. Assume the following scenario: - The driver Foo is used on SoC Bar and SoC Baz - The SoC Bar uses Device Tree control (CONFIG_OF_CONTROL=y) - The SoC Baz does not support Device Tree; uses a board file In this situation, the device driver Foo should work with/without the device tree control. The driver should have .of_match and .ofdata_to_platdata members for SoC Bar, while they are meaningless for SoC Baz; therefore those device-tree control code should go inside #ifdef CONFIG_OF_CONTROL. The driver code will be like this: #ifdef CONFIG_OF_CONTROL static const struct udevice_id foo_of_match = { { .compatible = "foo_driver" }, {}, } static int foo_ofdata_to_platdata(struct udevice *dev) { ... } #endif U_BOOT_DRIVER(foo_driver) = { ... .of_match = of_match_ptr(foo_of_match), .ofdata_to_platdata = of_match_ptr(foo_ofdata_to_platdata), ... } This idea has been borrowed from Linux. (In Linux, this macro is defined in include/linux/of.h) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: fix include guardMasahiro Yamada2014-10-22-0/+1
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: include <linker_lists.h> from platdata.h and uclass.hMasahiro Yamada2014-10-22-0/+3
| | | | | | | | | | | | | | | | | | The header files include/dm/platdata.h and include/dm/uclass.h use ll_entry_declare(); therefore they depend on include/linker_lists.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
| * linker_lists: include <linux/compiler.h>Masahiro Yamada2014-10-22-0/+2
| | | | | | | | | | | | | | | | The header file include/linker_lists.h uses __aligned(); therefore it depends on include/linux/compiler.h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: fix commentsMasahiro Yamada2014-10-22-3/+3
| | | | | | | | | | | | | | | | | | The struct udevice stands for a device, not a driver. The driver_info.name is a driver's name, which is referenced to bind devices. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Support loading kernel setup from a FITSimon Glass2014-10-22-0/+16
|/ | | | | | | | Add a new setup@ section to the FIT which can be used to provide a setup binary for booting Linux on x86. This makes it possible to boot x86 from a FIT. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-10-20-1/+325
|\
| * ls102x: Add support for secure boot and enable blob commandRuchika Gupta2014-10-16-0/+8
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+29
| | | | | | | | | | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: Add command for encapsulating/decapsulating blobsRuchika Gupta2014-10-16-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+15
| | | | | | | | | | | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+91
| | | | | | | | | | | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+45
| | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-0/+16
| | | | | | | | | | | | | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_sec : Move SEC CCSR definition to common includeRuchika Gupta2014-10-16-0/+88
| | | | | | | | | | | | | | | | | | Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/P1010RDB:Update RESET_VECTOR_ADDRESS for 768KB u-boot sizeRuchika Gupta2014-10-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for P1010 SPI Flash Secure boot target. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Modified subject to P1010RDB] Reviewed-by: York Sun <yorksun@freescale.com>
* | lcd: Fix build error with CONFIG_LCD_BMP_RLE8Simon Glass2014-10-16-0/+1
|/ | | | | | | | Add a block to avoid a build error with the variable declaration. Enable the option on sandbox to prevent an error being introduced in future. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-17 22:20:45 +0000