| Commit message (Collapse) | Author | Age | Lines |
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This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.
Following configs are affected in this patch:
CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>
This patch also updates documentation for few of above NAND configs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
merging of common platform code in following commit
commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform
+-----------------+-----------------------------------------------------------+
| Macro | Reason for removal |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so |
| | configuring GPMC chip-select for smallest allowable |
| | segment (GPMC_SIZE_16M) is enough. |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of |
| | 128MB (GPMC_SIZE_128M) |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR | Unused Macros |
| PISMO1_NAND | |
| PISMO2_CS0 | |
| PISMO2_CS1 | |
| PISMO1_ONENAND | |
| PISMO2_NAND_CS0 | |
| PISMO2_NAND_CS1 | |
| PISMO1_NOR_BASE | |
| PISMO1_NAND_BASE| |
| PISMO2_CS0_BASE | |
+-----------------+-----------------------------------------------------------+
Signed-off-by: Pekon Gupta <pekon@ti.com>
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Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform
1) NAND device are not directly memory-mapped to CPU address-space, they are
indirectly accessed via following GPMC registers:
- GPMC_NAND_COMMAND_x
- GPMC_NAND_ADDRESS_x
- GPMC_NAND_DATA_x
Therefore from CPU's point of view, NAND address-map can be limited to just
above register addresses. But GPMC chip-select address-map can be configured
in granularity of 16MB only.
So this patch uses GPMC_SIZE_16M for all NAND devices.
2) NOR device are directly memory-mapped to CPU address-space, so its
address-map size depends on actual addressable region in NOR FLASH device.
So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
size configuration.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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This patch adds Keystone2 k2e_evm evaluation board support.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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This patch adds clock definitions and commands to support Keystone2
K2E SOC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.
Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
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Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Thomas Weber <thomas.weber@corscience.de>
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Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
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The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.
The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.
The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.
Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.
Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
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As this is a weak function that we may override, provide a prototype for
it.
Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Add support for using the second slave port of cpsw
to be used as primary ethernet.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
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The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI,
MMC, SDHI and more.
This commit supports the following functions:
- DDR3-SDRAM
- SCIF
- I2C
- Ethernet
- QSPI
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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Similar to the USB NIC found on OMAP5uEVM, PandaBoard and BeagleBoard-XM
boards, the sunxi SoCs have a NIC onboard without an embedded MAC address.
Just like the omap used on these boards, the sunxi SoCs do have a unique chip
id, in the form of the 128 bit SID register:
http://linux-sunxi.org/SID_Register_Guide
So mimick the BeagleBoard-XM board code (commit 548a64d8) and use the chip id
to generate a unique fixed MAC address.
We check for the SID not being all 0, since some early A20 batches
shipped without having there SID programmed.
Note we use specific parts of the 128 bits, since some parts indicate the
SoC family / revision, and thus are fixed. The algorithm for this was taken
from the linux-sunxi.org kernels.
Signed-off-by: Jonathan Liu <net147@gmail.com>
[hdegoede@redhat.com: Expanded the commit message with some more info]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the x-powers axp152 pmic which is found on most A10s boards
and enable it for the r7-tv-dongle board.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the x-powers axp209 pmic which is found on most A10, A13 and
A20 boards.
And enable AXP209 support for the Cubietruck and Cubieboard boards.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
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Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).
The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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There have been 3 versions of the sunxi_emac support patch during its
development. Somehow version 2 ended up in upstream u-boot where as
the u-boot-sunxi git repo got version 3.
This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.
The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:
-Different hcpr values
-Different MBUS settings
-Some other small initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.
Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.
Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Enable CONFIG_SYS_GENERIC_BOARD for all Zynq boards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board]
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Some boards will have devices which are not in the device tree and do not
have platform data. They may be programnatically created, for example.
Add a hook which boards can use to bind those devices early in boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some devices (particularly bus devices) must track their children, knowing
when a new child is added so that it can be set up for communication on the
bus.
Add a child_pre_probe() method to provide this feature, and a corresponding
child_post_remove() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some device types can have child devices and want to store information
about them. For example a USB flash stick attached to a USB host
controller would likely use this space. The controller can hold
information about the USB state of each of its children.
The data is stored attached to the child device in the 'parent_priv'
member. It can be auto-allocated by dm when the child is probed. To
do this, add a per_child_auto_alloc_size value to the parent driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Devices can have childen that can be addressed by a simple index, the
sequence number or a device tree offset. Add functions to access a child
in each of these ways.
The index is typically used as a fallback when the sequence number is not
available. For example we may use a serial UART with sequence number 0 as
the console, but if no UART has sequence number 0, then we can fall back
to just using the first UART (index 0).
The device tree offset function is useful for buses, where they want to
locate one of their children. The device tree can be scanned to find the
offset of each child, and that offset can then find the device.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present only root nodes in the device tree are scanned for devices.
But some devices can have children. For example a SPI bus may have
several children for each of its chip selects.
Add a function which scans subnodes and binds devices for each one. This
can be used for the root node scan also, so change it.
A device can call this function in its bind() or probe() methods to bind
its children.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Fix up the style of a few comments and add/clarify a few others.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This simple function returns the node offset of a named alias.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Each device that was bound from a device tree has an node that caused it to
be bound. Add functions that find and return a device based on a device tree
offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.
Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.
With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.
Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.
At present there is no support for sequence numbers using static platform
data. It could easily be added to 'struct driver_info' if needed, but it
seems better to add features as we find a use for them, and the use of -1
to mean 'no sequence' makes the default value somewhat painful.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Aliases are used to provide U-Boot's numbering of devices, such as:
aliases {
spi0 = "/spi@12330000";
}
spi@12330000 {
...
}
This tells us that the SPI controller at 12330000 is considered to be the
first SPI controller (SPI 0). So we have a numbering for the SPI node.
Add a function that returns the numbering for a node assume that it exists
in the list of aliases.
Signed-off-by: Simon Glass <sjg@chromium.org>
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For sandbox we have a fallback console which is used very early in
U-Boot, before serial drivers are available. Rather than try to guess
when to switch to the real console, add a flag so we can be sure. This
makes sure that sandbox can always output a panic() message, for example,
and avoids silent failure (which is very annoying in sandbox).
Signed-off-by: Simon Glass <sjg@chromium.org>
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The current functions for adding and removing devices require a device name.
This is not convenient for driver model, which wants to store a pointer to
the relevant device. Add new functions which provide this feature and adjust
the old ones to call these.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Initialise devices marked 'pre-reloc' and make them available prior to
relocation. Note that this requires pre-reloc malloc() to be available.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Driver model currently only operates after relocation is complete. In this
state U-Boot typically has a small amount of memory available. In adding
support for driver model prior to relocation we must try to use as little
memory as possible.
In addition, on some machines the memory has not be inited and/or the CPU
is not running at full speed or the data cache is off. These can reduce
execution performance, so the less initialisation that is done before
relocation the better.
An immediately-obvious improvement is to only initialise drivers which are
actually going to be used before relocation. On many boards the only such
driver is a serial UART, so this provides a very large potential benefit.
Allow drivers to mark themselves as 'pre-reloc' which means that they will
be initialised prior to relocation. This can be done either with a driver
flag or with a 'dm,pre-reloc' device tree property.
To support this, the various dm scanning function now take a 'pre_reloc_only'
parameter which indicates that only drivers marked pre-reloc should be
bound.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a new method which removes and unbinds all drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
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At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.
For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.
Instead, add a stdio_dev pointer to each of the stdio member functions.
Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.
Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.
22: stdio: Pass device pointer to stdio methods
arm: (for 2/2 boards) all +244.0 bss -4.0 text +248.0
powerpc: (for 1/1 boards) all +428.0 text +428.0
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
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Enable this for sandbox so that we will be able to use driver model before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
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If we are to have driver model before relocation we need to support some
way of calling memory allocation routines.
The standard malloc() is pretty complicated:
1. It uses some BSS memory for its state, and BSS is not available before
relocation
2. It supports algorithms for reducing memory fragmentation and improving
performace of free(). Before relocation we could happily just not support
free().
3. It includes about 4KB of code (Thumb 2) and 1KB of data. However since
this has been loaded anyway this is not really a problem.
The simplest way to support pre-relocation malloc() is to reserve an area
of memory and allocate it in increasing blocks as needed. This
implementation does this.
To enable it, you need to define the size of the malloc() pool as described
in the README. It will be located above the pre-relocation stack on
supported architectures.
Note that this implementation is only useful on machines which have some
memory available before dram_init() is called - this includes those that
do no DRAM init (like tegra) and those that do it in SPL (quite a few
boards). Enabling driver model preior to relocation for the rest of the
boards is left for a later exercise.
Signed-off-by: Simon Glass <sjg@chromium.org>
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