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* Add a command to read raw blocks from a partitionKenneth Waters2012-12-11-0/+1
| | | | | | | | | | Sometimes data is on a block device and within a partition, but not in a particular filesystem. This commands permits reading raw data from a partition. Signed-off-by: Kenneth Waters <kwaters@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Add gettime commandAnton Staaf2012-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Gettime returns the current timer value. If CONFIG_SYS_HZ is defined then the timer value is also converted to seconds. Tegra20 (SeaBoard) # gettime Timer val: 7754 Seconds : 7 Remainder : 754 sys_hz = 1000 There has been some discussion about whether this is useful enough to be included in U-Boot. The following boards do not have CONFIG_SYS_HZ defined: M52277EVB M52277EVB_stmicro M53017EVB M54418TWR M54418TWR_nand_mii M54418TWR_nand_rmii M54418TWR_nand_rmii_lowfreq M54418TWR_serial_mii M54418TWR_serial_rmii Signed-off-by: Anton Staaf <robotboy@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* gpio: remove duplicate function signatureNikita Kiryanov2012-12-11-13/+4
| | | | | | | gpio_request() appears twice in asm-generic/gpio.h Remove one of the definitions. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-07-17/+175
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| * x86: Fix coreboot config to boot on ChromebookSimon Glass2012-12-06-14/+12
| | | | | | | | | | | | | | | | | | | | The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Turn on support for EFI's GPT in the coreboot configGabe Black2012-12-06-0/+3
| | | | | | | | | | | | | | This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Enable video displaySimon Glass2012-12-06-2/+8
| | | | | | | | | | | | Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-06-1/+1
| | | | | | | | | | | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * Introduce arch_phys_memset which works like memset but on physical memoryGabe Black2012-12-06-0/+21
| | | | | | | | | | | | | | | | | | | | The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass2012-12-06-0/+3
| | | | | | | | | | | | Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable ICH6 GPIO controller for corebootSimon Glass2012-12-06-0/+4
| | | | | | | | | | | | Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+123
| | | | | | | | | | | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Change e-mail address of Luka PerkovLuka Perkov2012-12-07-2/+2
| | | | | | | | | | | | | | Change e-mail address of Luka Perkov. Signed-off-by: Luka Perkov <luka@openwrt.org> CC: Luka Perkov <uboot@lukaperkov.net>
* | cbfs: Add docbook templateSimon Glass2012-12-06-33/+36
| | | | | | | | | | | | This adds a docbook template for fs, and makes CBFS use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | cbfs: Remove mention of CREDITS filesSimon Glass2012-12-06-3/+0
|/ | | | | | | As requested by Wolfgang, remove references to CREDITS in the CBFS files. Signed-off-by: Simon Glass <sjg@chromium.org>
* 4xx: Fix PCI memory mapping on CPCI405 boardsMatthias Fuchs2012-12-06-4/+4
| | | | | | | | This patch fixes an issue with overlapping PCI regions on boards with more than 64MB RAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc5200: Add a3m071 board supportStefan Roese2012-12-05-0/+380
| | | | | | | This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-03-0/+16
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| * x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass2012-11-30-0/+1
| | | | | | | | | | | | This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Select stdio devices for corebootSimon Glass2012-11-30-0/+12
| | | | | | | | | | | | | | We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add CBMEM console driver for corebootVadim Bendebury2012-11-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds upon the recently introduced CBMEM console feature of coreboot. CBMEM console uses a memry area allocated by coreboot to store the console output. The memory area has a certain structure, which allows to determine where the buffer is, the buffer size and the location of the pointer in the buffer. This allows different phases of the firmware (rom based coreboot, ram based coreboot, u-boot after relocation with this change) to keep adding text to the same buffer. Note that this patch introduces a new console driver and adds the driver to the list of drivers to be used for console output, i.e. it engages only after u-boot relocates. Usiong CBMEM console for capturing the pre-relocation console output will be done under a separate change. >From Linux, run the cbmem.py utility (which is a part of the coreboot package) to see the output, e.g.: vvvvvvvvvvvvvvvvv SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode flags: 64bit ilck stag led pmp pio ... Magic signature found Kernel command line: "cros_secure quiet loglevel=1 console=tty2... ^^^^^^^^^^^^^^^^^ Note that the entire u-boot output fits into the buffer only if the coreboot log level is reduced from the most verbose. Ether the buffer size will have to be increased, or the coreboot verbosity permanently reduced. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | include/linux/byteorder: Always defines __fswab64, __swab64p and __swab64sNobuhiro Iwamatsu2012-11-30-2/+0
|/ | | | | | | | | | | | | | | | | | When __BYTEORDER_HAS_U64__ is not defined, we got warning following: ----- /tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’: /tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’ [-Wimplicit-function-declaration] ----- Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary. This removes __BYTEORDER_HAS_U64__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-x86Tom Rini2012-11-28-10/+7
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| * x86: coreboot: Enable LPC TPMSimon Glass2012-11-28-0/+4
| | | | | | | | | | | | Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Remove coreboot start16 codeSimon Glass2012-11-28-1/+1
| | | | | | | | | | | | | | Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Put global data on the stackGraeme Russ2012-11-28-9/+2
| | | | | | | | | | | | | | | | | | | | Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2012-11-28-8/+60
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| * powerpc/corenet_ds: move SATA config to board configurationZang Roy-R619112012-11-27-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/P2041RDB: Fix Flash address LAW addressYork Sun2012-11-27-4/+10
| | | | | | | | | | | | | | | | | | P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-0/+40
| | | | | | | | | | | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/qoriq: Move FMAN microcode locationYork Sun2012-11-27-3/+3
| | | | | | | | | | | | | | | | | | Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: tegra: use bounce buffer APIsStephen Warren2012-11-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | common: rework bouncebuf implementationStephen Warren2012-11-27-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current bouncebuf API requires all parameters to be passed to both bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf start function to accept a state structure as a parameter, and only require that state struct to be passed to the stop function. This simplifies usage of the bounce buffer by clients. Don't modify the data pointer, but rather store the temporary buffer in this state struct. The bouncebuf code ensures that client code can always use a single buffer pointer in the state structure, irrespective of whether a bounce buffer actually had to be allocated. Move cache management logic into the bounce buffer code, so that each client doesn't have to duplicate this. I believe there's no need to invalidate the buffer before a DMA operation, since flushing the cache should prevent any write-backs. Update the MXS MMC driver for this change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | bouncebuf: remove dummy implementationStephen Warren2012-11-27-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | If any driver ever needs to use the bounce buffer API, it always needs to use it. As such, providing a dummy implementation of those APIs when CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Replace CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER in configsStephen Warren2012-11-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed converting a few boards over to the new option. Fix this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: add no simultaenous power and vddMela Custodio2012-11-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the code from Linux kernel. Added to Linux kernel by: commit e08c1694d9e2138204f2b79b73f0f159074ce2f5 Author: Andres Salomon <dilinger@queued.net> Date: Fri Jul 4 10:00:03 2008 -0700 Some HW balks when writing both voltage setting and power up at the same time to SDHCI_POWER_CONTROL register. Signed-off-by: Rommel G Custodio <sessyargc@gmail.com> CC: Andy Fleming <afleming@freescale.com> v2: fix attribution and SOB Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: at91sam9x5: support to save environment in mmcWu, Josh2012-11-27-3/+16
|/ | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Remove obsolete header filePantelis Antoniou2012-11-27-1/+0
| | | | | | | usbdescriptors.h conflicts with linux/usb/ch9.h Remove it. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2012-11-26-74/+113
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| * nand: Add torture featureBenoît Thébaudeau2012-11-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a NAND Flash torture feature, which is useful as a block stress test to determine if a block is still good and reliable (or should be marked as bad), e.g. after a write error. This code is ported from mtd-utils' lib/libmtd.c. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: Move the sub-page read support enable to a flagJoe Hershberger2012-11-26-3/+4
| | | | | | | | | | | | | | | | | | Use a flag instead of a hard-coded macro so that sub-page reads can be enabled in other cases (such as on-die ecc). This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL bootScott Wood2012-11-26-36/+33
| | | | | | | | | | | | | | | | | | | | | | | | This allows DDR configuration to be deferred to the final U-Boot image, which is able to make use of SPD data. The SPL itself cannot use SPD due to code size constraints. It previously used fixed register values for DDR configuration, and those values did not work on the p2020rdb-pca board I tested with. It's possible that different revisions of the board require different settings. Using SPD eliminates that problem. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory mapScott Wood2012-11-26-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Sort by address, and fix column alignment - Don't label things as localbus that aren't. Instead, put chipselect info at the end of the description for localbus windows. Note that NAND/NOR have their chipselects swapped when booting from NAND, and CS2 can be either PMC or VSC7385 depending on hwconfig. - Shrink NAND to the 32K that's actually mapped in the localbus - Assign an address and size to L2 SRAM. Remove the similarly named but unintelligible "L2 SDRAM(REV.)". - Remove the untrue comment about L1 stack being mapped with TLB0. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new splScott Wood2012-11-26-26/+28
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.Scott Wood2012-11-26-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some small SPLs do not use nand_base.c, and a subset of those also require a special driver. Some SPLs need software ECC but others can't fit it. All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these symbols added to preserve existing behavior. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: use positive logic for including bits of NAND, rather than a MINIMAL symbol that excludes things.
* | Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2012-11-20-0/+113
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| * \ Merge branch 'next'Gerald Van Baren2012-11-19-0/+113
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| | * fdt: Add option to default to most compatible conf in a fit imageGabe Black2012-11-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a fit image with multiple configurations, the user either has to specify which configuration to use explicitly, or there has to be a default defined which is chosen automatically. This change adds an option to change that behavior so that a configuration can be selected explicitly, or the configuration which has the device tree that claims to be compatible with the earliest item in U-Boot's device tree. In other words, if U-Boot claimed to be compatible with A, B, and then C, and the configurations claimed to be compatible with A, D and B, D and D, E, the first configuration, A, D, would be chosen. Both the first and second configurations match, but the first one matches a more specific entry in U-Boot's device tree. The order in the kernel's device tree is ignored. Signed-off-by: Gabe Black <gabeblack@google.com> Commit-Ready: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Add polarity-aware gpio functions to fdtdecSean Paul2012-11-12-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Add get and set gpio functions to fdtdec that take into account the polarity field in fdtdec_gpio_state.flags. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Add fdtdec_get_uint64 to decode a 64-bit value from a propertyChe-Liang Chiou2012-11-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | It decodes a 64-bit value from a property that is at least 8 bytes long. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-05 14:50:58 +0000