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* include/fsl_usb.h: Cleanup license headerYork Sun2013-08-14-17/+1
| | | | | | | | Replace license header with SPDX license identifier. Replace GPL-2.0 with GPL-2.0+. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-14-0/+80
| | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-13-586/+1849
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| * powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-51/+3
| | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/c29xpcie: add support for C29XPCIE boardMingkai Hu2013-08-09-0/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha2013-08-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * p1020rdb-pd: platform supportHaijun.Zhang2013-08-09-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-0/+1
| | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/T4240EMU: Add T4240EMU targetYork Sun2013-08-09-504/+727
| | | | | | | | | | | | | | | | | | | | | | | | Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/t4qds: cleanup board header fileYork Sun2013-08-09-68/+0
| | | | | | | | | | | | CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-09-4/+0
| | | | | | | | | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/85xx: Add TWR-P10xx board supportXie Xiaobo2013-08-09-0/+635
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-videoTom Rini2013-08-12-6/+2166
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| * | edid: rename struct member to fix two EDID_* macrosChristian Gmeiner2013-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this change EDID_DETAILED_TIMING_VSYNC_OFFSET and EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH macros can not be used (compile error). The fix is quite trivial: rename struct member to the expected name. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | video: Add small 4x6 font from LinuxMarek Vasut2013-08-12-0/+2158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This font is based on Linux drivers/video/console/font_mini_4x6.c as of commit: commit bcfbeecea11c15e243f076d37d637c2598aff4fe Author: Bjarni Ingi Gislason <bjarniig@rhi.hi.is> Date: Sun Aug 12 15:05:10 2012 +0000 drivers: console: font_: Change a glyph from "broken bar" to "vertical line" I removed these lines as they are useless in U-Boot: #include <linux/font.h> #define FONTDATAMAX 1536 Whole "const struct font_desc font_mini_4x6" block This patch also adds a new configuration option to select this smaller font, CONFIG_VIDEO_FONT_4X6 , but this is disabled by default. The default setting is the regular "large" font. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
| * | video: Encapsulate font in video_font_data.hMarek Vasut2013-08-12-5/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch moves all the font configuration values into video_font_data.h so they are all in the right place with the font. The video_font.h now only includes video_font_data.h and will allow us to select and include different font once more fonts are added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> [agust: fixed build warning for mcc200] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mpc5200: Misc updates to a3m071 config headerStefan Roese2013-08-12-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | This patch changes some features of the a3m071/a4m2k board support: - Add bootcounter support - Update MTD env default to correct values - Add mtdparts to bootargs for mtd partitioning via kernel cmdline - Added some default env variables for easy updating (kernel, dtb) - Change README to the updated flash locations Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2013-08-12-0/+5
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| * | fpga: zynqpl: Add support for zc7100 device.Michal Simek2013-08-12-0/+5
| |/ | | | | | | | | | | | | | | | | | | - Add support for zc7100 device. - FPGA programming on few of the SOC(zc7100) takes more than 1sec, hence increased the program time by 4sec to sync' all soc's. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: Enable CONFIG_ZYNQ_SPIJagannadha Sutradharudu Teki2013-08-07-0/+9
|/ | | | | | | | | | | | Tested spi on zynq board with sst flash by enabling CONFIG_ZYNQ_SPI. sf probe 1:1 0 0 SF: Detected SST25WF080 with page size 4 KiB, total 1 MiB Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-08-06-2/+2
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| * i2c: soft: Fix typo in CONFIG_SYS_I2C_SOFT_SPEEDMarek Vasut2013-08-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case only the CONFIG_SYS_I2C_SPEED is set in configuration file, the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED. The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver. Unfortunatelly, due to a typo in the driver, instead of defining CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined and therefore the driver failed to compile. The same applies for CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | config: don't define CONFIG_ARCH_DEVICE_TREEStephen Warren2013-08-02-1/+0
| | | | | | | | | | | | | | Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | xilinx: move microblaze-generic .dts to standard locationStephen Warren2013-08-02-1/+1
|/ | | | | | | | | | Aside from microblaze, all other SoCs/boards/vendors store their DT files in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this location for consistency. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <monstr@monstr.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-08-01-47/+43
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| * dfu: Implementation of target reset after communication with dfu-util's -R ↵Lukasz Majewski2013-07-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | switch This patch extends dfu code to support transmission with -R switch specified at dfu-util. When -R is specified, the extra USB_REQ_DFU_DETACH request is sent after successful data transmission. Then dfu resources are released and reset command is issued. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * usb: mv_udc: Add bounce bufferMarek Vasut2013-07-29-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | The requests sent to the controller are not properly cache aligned most of the time, thus implement a simple bounce buffer to avoid problem with cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Improve allocation of qTD itemsMarek Vasut2013-07-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Allocate the qTD items all at once instead of allocating them separately. Moreover, make sure each qTD is properly aligned to 32-bytes boundary and that cache can be safely flushed over each qTD touple. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Move QH and qTD into mv_drvMarek Vasut2013-07-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | Both the endpoint queue head and the endpoint item list is a controller specific thing. Move them both into controller private data. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Make use of struct ehci_ctrlMarek Vasut2013-07-29-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb_lowlevel_init() call already fills and passes back struct ehci_ctrl , which readily contains correctly determined address of the port register block address computed from values from controller configuration registers. Leverage this and make use of this value as this makes the code mode universal, but also gets us rid of the CONFIG_USB_REG_BASE configuration option. Moreover, this patch cleans up the usb_gadget_register_driver() call a little by correcting the error handling. Note the usb_lowlevel_init() and mvudc_probe() are now called in reversed order, but this has no impact on the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Clean up the EP initializationMarek Vasut2013-07-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the constant values that are programmed into mv_ep.ep into separate static const structure so they can be memcpy()'d when the initialization happens. Moveover, we only every init NUM_ENDPOINTS, not 2 * NUM_ENDPOINTS, so fix this bug as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Move endpoint array into driver dataMarek Vasut2013-07-29-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | The endpoints are operated on a per-controller basis, move the endpoint array into controller's private data. Also shuffle the struct mv_ep structure definition just above the definition of the struct mv_drv so they're well grouped together. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Clean up mv_udc.hMarek Vasut2013-07-29-37/+23
| | | | | | | | | | | | | | | | | | | | | | | | Do a coding-style cleanup of this file and throw away useless defined values. These values were likely a result of a copy-paste job. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | cfi_flash: Add prototypes of overridable functionsMasahiro Yamada2013-07-30-0/+14
|/ | | | | | | | | | | | | | | | This commit adds some prototypes into include/mtd/cfi_flash.h. These functions are defined with a weak attribute in drivers/mtd/cfi_flash.c. This means they can be overrided by board-specific ones if necessary. When defining such functions under board/ directory or somewhere, cfi_flash.h should be included. This makes sure that board-specfic cfi functions are defined in a correct prototype. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boardsDirk Eibach2013-07-25-10/+5
| | | | | | | | | | | CONFIG_SYS_FLASH_PROTECTION was active on most gdsys boards by default, while hardware flash protection was not implemented. Hardware support was added recently and we get into trouble because backward compatibility is broken (u-boot can't unprotect the protected flash after a downgrade). So we decided to disable hardware flash protection for all our boards. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc/ppc4xx: Support gdsys multichannel iocon hardwareDirk Eibach2013-07-25-14/+59
| | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc/ppc4xx: Use generic accessor functions for gdsys FPGADirk Eibach2013-07-25-8/+62
| | | | | | | | | | A set of accessor functions was added to be able to access not only memory mapped FPGA in a generic way. Thanks to Wolfgang Denk for getting this sorted properly. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2013-07-25-3/+121
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| * nds32: Enable the function of passing parameters to Linuxken kuo2013-07-24-0/+15
| | | | | | | | | | | | | | | | | | Add a header file, setup.h, which copy from Linux source code, this file contain structures are used to pass initialisation parameters to Linux. Enable this function on adp-ag101/adp-ag101p target Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: Enable SDIO and EXT2 command support for Andes boardken kuo2013-07-24-0/+4
| | | | | | | | | | Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: Enable two banks of SDRAM on Andes boardken kuo2013-07-24-2/+17
| | | | | | | | | | | | | | | | | | The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * pci: move pci_ftpci100.h to include/faraday/ftpci100.hGabor Juhos2013-07-24-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the header files is used only by the pci_ftpci100 driver, it contains declaration for a function which is used by external code. Move the header file to a common location which lets external code use it. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| * block: constify sect_buf argument of ide_write_dataGabor Juhos2013-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a const keyword to the sect_buf argument of ide_write_data to fix the following warning: cmd_ide.c: In function '__ide_output_data': cmd_ide.c:548: warning: passing argument 2 of 'ide_write_data' discards qualifiers from pointer target type /devel/u-boot.git/include/ide.h:76: note: expected 'ulong *' but argument is of type 'const ulong *' Also modify the driver-model documentation to match with the new prototype. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* | qemu-malta: Update for SPDX license identifiersTom Rini2013-07-25-18/+3
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-07-25-0/+685
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflict over SPDX changes means that one change was effectively dropped as it was fixing typos in a removed hunk of text. Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
| * | MIPS: qemu-malta: bring up ethernetGabor Juhos2013-07-24-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu emulates a PCNET PCI card for the Malta CoreLV board. Enable the pcnet driver and add board specific ethernet initialization function to bring it up. Also enable the CONFIG_CMD_NET and CONFIG_CMD_PING options. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: qemu-malta: add PCI supportGabor Juhos2013-07-24-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
generated by cgit v1.1 at 2024-11-19 09:34:54 +0000