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* arm: socfpga: DW_SPI: Remove clock info from config headerStefan Roese2014-12-06-4/+0
| | | | | | | | | | | | | Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiersStefan Roese2014-12-06-8/+1
| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add Designware (DW) SPI support to config headerStefan Roese2014-12-06-0/+12
| | | | | | | | | | | | | Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add Cadence QSPI support to config headerStefan Roese2014-12-06-1/+24
| | | | | | | | | | | | | | | | | | | | With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2014-12-01-11/+0
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| * fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada2014-11-27-11/+0
| | | | | | | | | | | | | | | | | | | | The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-01-22/+460
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| * | x86: chromebook_link: Enable the Chrome OS ECSimon Glass2014-11-25-0/+5
| | | | | | | | | | | | | | | | | | Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: chromebook_link: Enable the x86 emulatorSimon Glass2014-11-25-0/+4
| | | | | | | | | | | | | | | | | | Enable this so that it can be used instead of native execution if desired. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | bios_emulator: Add vesa support and allow ROMs to be passed in as dataSimon Glass2014-11-25-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | As well as locating the ROM on the PCI bus, allow the ROM to be supplied to the emulator. Split the init up a little so that callers can supply their own interrupt routines. Also allow a vesa mode to be provided, to be selected once the BIOS run is complete. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable video support for chromebook_linkSimon Glass2014-11-25-7/+3
| | | | | | | | | | | | | | | | | | | | | Now that we have the required drivers, enable video support with a suitable option ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add initial video device init for Intel GMASimon Glass2014-11-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pci: Add general support for execution of video ROMsSimon Glass2014-11-25-1/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms don't have native code for dealing with their video hardware. In some cases they use a binary blob to set it up and perform required actions like setting the video mode. This approach is a hangover from the old PC days where a ROM was provided and executed during startup. Even now, these ROMs are supplied as a way to set up video. It avoids the code for every video chip needing to be provided in the boot loader. But it makes the video much less flexible - e.g. it is not possible to do anything else while the video init is happening (including waiting hundreds of milliseconds for display panels to start up). In any case, to deal with this sad state of affairs, provide an API for execution of x86 video ROMs, either natively or through emulation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Add support for Vesa BIOS extensionsSimon Glass2014-11-25-0/+103
| | | | | | | | | | | | | | | | | | | | | For option ROMs we can use these extensions to request a particular video mode. Add a header file which defines the binary interface. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Introduce a header file for the BIOS emulatorSimon Glass2014-11-25-0/+43
| | | | | | | | | | | | | | | | | | | | | We should have a public header so that users can avoid defining functions themselves. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a definition of asmlinkageSimon Glass2014-11-25-0/+3
| | | | | | | | | | | | | | | | | | | | | This is needed to permit calling C from assembler without too much pain. Add a definition for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable SPI for chromebook_linkSimon Glass2014-11-25-4/+0
| | | | | | | | | | | | | | | | | | Enable SPI so that the SPI flash can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | | | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: config: Enable USB on linkSimon Glass2014-11-25-2/+0
| | | | | | | | | | | | | | | | | | Enable USB support on link - there are two EHCI ports available. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add SATA settings for linkSimon Glass2014-11-25-1/+0
| | | | | | | | | | | | | | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pci: Add functions to read and write a BAR addressSimon Glass2014-11-25-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: config: Enable plug-and-play for link PCISimon Glass2014-11-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Enable this option so that we can configure the available PCI devices. Also make sure that PCI is available early after relocation as we use it for several other subsystems. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rtc: mc146818: Set up RTC at start of daySimon Glass2014-11-25-0/+5
| | | | | | | | | | | | | | | | | | | | | Provide a function to set up the RTC ready for use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Remove board_early_init_r()Simon Glass2014-11-25-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | pci: Update pci_ids.h to include some missing IDsSimon Glass2014-11-25-6/+181
| | | | | | | | | | | | | | | | | | | | | This was taken from Linux 3.18 with some additional IDs from Chrome OS Coreboot commit 688ef385. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Fix SIZE_MAX compiler warning when using stdint.hSimon Glass2014-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | This new symbol may be defined by the compiler. If it is, avoid a compiler warning when USE_STDINT is defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-27-15/+0
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| * | | ARM: UniPhier: move CONFIG_CMD_* and CONFIG_FIT* defines to defconfigMasahiro Yamada2014-11-28-15/+0
| | |/ | |/| | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | MIPS: vct: switch to generic boardDaniel Schwierzeck2014-11-27-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | MIPS: qemu_mips: switch to generic boardDaniel Schwierzeck2014-11-27-0/+6
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | MIPS: pb1x00: switch to generic boardDaniel Schwierzeck2014-11-27-0/+3
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | MIPS: dbau1x00: switch to generic boardDaniel Schwierzeck2014-11-27-0/+3
|/ / | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-0/+123
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| * | arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: ifc: nor: fix the write issue when bytes unalignedYuan Yao2014-11-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add define CONFIG_SYS_WRITE_SWAPPED_DATA. For LS1021AQDS and LS1021QTWR nor flash write should swap the bytes when handle unaligned tail bytes. Because of the ending, if the date bus width is 16-bits and the number of bytes is odd, we should swap the byte when write the last one. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1: config: Enable USB EHCI Host on LS1021AQDSNikhil Badola2014-11-24-0/+17
| | | | | | | | | | | | | | | | | | | | | Enable USB EHCI Host on LS1021AQDS Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Define USB configs for LS102XANikhil Badola2014-11-24-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers : usb: fsl: Implement usb Erratum A007798 workaroundNikhil Badola2014-11-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Move USB Errata checking codeNikhil Badola2014-11-21-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move USB Errata checking code from "arch/powerpc" to architecture independent file "fsl_usb.h" so that errata(s) become independent of the architecture. For each erratum checking function for PPC arch, define a nop function for non PPC arch for successful compilation in either case Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | qe: add qe support for ls1021a-twr boardZhao Qiang2014-11-19-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | qe: add qe support to ls1021aqdsZhao Qiang2014-11-19-0/+7
| | | | | | | | | | | | | | | | | | | | | add qe support to ls1021aqds Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-11-26-1/+56
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/mmc/fsl_esdhc.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | net/fm: add 2.5G SGMII supportShengzhou Liu2014-11-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As auto-negotiation is not supported for 2.5G SGMII, we need to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate SGMII-1G and SGMII-2.5G with different setting for auto-negotiation. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | config: MPC837X : Add complete USB EHCI supportNikhil Badola2014-11-19-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add complete USB EHCI support for MPC837XEMDS and MPC837XERDB Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t4rdb: Fix CPLD timingChunhe Lan2014-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes CPLD timing from previous commit ab06b236f76cfa42f264ee161be190b3e479298f. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: This is the difference between v2 and v1 patch] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | P1023RDB: Update default environmentChunhe Lan2014-11-19-0/+43
| |/ / | | | | | | | | | | | | Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2014-11-26-56/+167
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| * | | ORIGEN: Enhance origen config to be more flexible on boot.Guillaume GARDET2014-11-25-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the boot of origen board by adding support to ext2, bootz, initrd, bootenv loading and boot script. It still keeps the previous mmc load command if boot script fails. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | arm: odroid: usb: add support for usb host including ethernetSuriyan Ramasami2014-11-17-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for enabling the USB host features of the board. This includes the USB3503A hub and the SMC LAN9730 ethernet controller as well. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-10 07:23:11 +0000