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* ppc4xx: Fix 460EX errata with CPU lockup upon high AHB trafficStefan Roese2008-06-30-0/+2
| | | | | | | | | | | | | | | This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix 4xx build issueAnatolij Gustschin2008-06-19-1/+1
| | | | | | | | | | | | | | Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Change lmb to use phys_size_t/phys_addr_tBecky Bruce2008-06-12-11/+13
| | | | | | | | | | | This updates the lmb code to use phys_size_t and phys_addr_t instead of unsigned long. Other code which interacts with this code, like getenv_bootm_size() is also updated. Booted on MPC8641HPCN, build-tested ppc, arm, mips. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Change print_size to take phys_size_tBecky Bruce2008-06-12-1/+1
| | | | Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Change bd/gd memsize/ram_size to be phys_size_t.Becky Bruce2008-06-12-20/+20
| | | | | | | | | | Currently, both are defined as an unsigned long, but should be phys_size_t. This should result in no real change, since phys_size_t is currently an unsigned long for all the default configs. Also add print_lnum to cmd_bdinfo to deal with the potentially wider memsize. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-shWolfgang Denk2008-06-11-0/+179
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| * sh: Renesas Solutions SH7763RDP board supportNobuhiro Iwamatsu2008-06-09-0/+126
| | | | | | | | | | | | | | | | SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC. In this patch, support SCIF, NOR Flash, and Ethernet. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add support Renesas SH7763Nobuhiro Iwamatsu2008-06-09-0/+53
| | | | | | | | | | | | | | | | Renesas SH7763 has 3 SCIF, MMC, LCDC, Ethernet and other. This patch supprts CPU register's header file. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk2008-06-11-68/+164
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| * | [MIPS] Rename Alchemy processor configs into CONFIG_SOC_*Shinya Kuribayashi2008-06-07-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SOC_AU1X00 Common Alchemy Au1x00 stuff. All Alchemy processor based machines need to have this config as a system type specifier. CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 Machine type specifiers. Each port should have one of aboves. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | [MIPS] Update <asm/addrspace.h> headerShinya Kuribayashi2008-06-05-44/+127
| | | | | | | | | | | | | | | | | | | | | - Fix traditional KSEG names - Replace PHYSADDR with CPHYSADDR Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * | [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routinesShinya Kuribayashi2008-06-05-7/+20
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS port has two problems in timer routines. One is now we assume CFG_HZ equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000 in the U-Boot system. The other is we don't have a proper time management counter like timestamp other ARCHs have. We need the 32-bit millisecond clock counter. This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a 32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number of calculated CP0 counter cycles in a CFG_HZ. STRATEGY: * Fix improper CFG_HZ value to have 1000 * Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead. * timer_init: initialize timestamp and set up the first timer expiration. Note that we don't need to initialize CP0 count/compare registers here as they have been already zeroed out on the system reset. Leave them as they are. * get_timer: calculate how many timestamps have been passed, then return base-relative timestamp. Make sure we can easily count missed timestamps regardless of CP0 count/compare value. * get_ticks: return the current timestamp, that is get_timer(0). Most parts are from good old Linux v2.6.16 kernel. v2: - Remove FIXME comments as they turned out to be trivial. - Use CP0 compare register as a global variable for expirelo. - Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY instead. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-fdtWolfgang Denk2008-06-11-75/+5
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| * | fdt: unshadow global working fdt variableKim Phillips2008-06-10-1/+1
| | | | | | | | | | | | | | | | | | | | | differentiate with local variables of the same name by renaming the global 'fdt' variable 'working_fdt'. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | Remove the deprecated CONFIG_OF_FLAT_TREEGerald Van Baren2008-06-09-71/+1
| | | | | | | | | | | | | | | | | | | | | Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is cleaner, has better functionality, and is better supported. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
| * | Change the stxxst to CONFIG_OF_LIBFDTGerald Van Baren2008-06-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: It appears that this board lost its ability to boot via a flattened device tree prior to this changeset. WARNING: This conversion was untested because I do not have a board to test it on. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
| * | Convert mpc7448hpc2 to CONFIG_OF_LIBFDTGerald Van Baren2008-06-09-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: This conversion is untested because I do not have a board to test it on. NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) /aliases/ethernet1 property for the ethernet to work. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-netWolfgang Denk2008-06-11-9/+2
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| * \ Merge branch 'master' of git://git.denx.de/u-bootBen Warren2008-06-08-646/+3856
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| * | DM9000: Add data bus-width auto detection.Remy Bohmer2008-06-04-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The U-boot DM9000x driver contains a compile time bus-width definition for the databus connected to the network controller. This compile check makes the code unclear, inflexible and is unneccessary. It can be asked to the network controller what its bus-width is by reading bits 6 and 7 of the interrupt status register. The linux kernel already uses a runtime mechanism to determine this bus-width, so the implementation below looks somewhat like that implementation. This change has been tested with DM9000A, DM9000E, DM9000EP. Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-bootBen Warren2008-06-02-7/+27
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| * | | E1000: Add support for the 82541GI LF Intel Pro 1000 GT Desktop AdapterWolfgang Grandegger2008-06-02-1/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-06-11-3715/+2038
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| * | | | ppc4xx: Unify AMCC's board config files (part 3/3)Stefan Roese2008-06-06-999/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Unify AMCC's board config files (part 2/3)Stefan Roese2008-06-06-1298/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Unify AMCC's board config files (part 1/3)Stefan Roese2008-06-06-0/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Cleanup CPCI405 variant's config fileMatthias Fuchs2008-06-03-93/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes some dead code from CPCI405 board's config files. JFFS2 support is also removed. It's not used and CPCI4052 does not build anymore without some size reduction. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | | | ppc4xx: Remove implementations of testdram()Stefan Roese2008-06-03-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the used testdram() implementations of the board that are maintained by myself. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese2008-06-03-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part2Stefan Roese2008-06-03-0/+1156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch now adds a new header file (asm-ppc/ppc4xx-sdram.h) for all ppc4xx related SDRAM/DDR/DDR2 controller defines. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1Stefan Roese2008-06-03-1310/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-27/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 2 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-15/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-06-03-6240/+6702
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* | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-06-11-109/+432
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/asm-ppc/fsl_lbc.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | | FSL LAW: Add new interface to use the last free LAWKumar Gala2008-06-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LAWs have the concept of priority so its useful to be able to allocate the lowest (highest number) priority. We will end up using this with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-11-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | 85xx: remove dummy board_early_init_fKumar Gala2008-06-11-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A number of board ports have empty version of board_early_init_f for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | MPC8544DS: Update config.hKumar Gala2008-06-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Enable flash progress * remove CLEAR_LAW0 since we dont really use it Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | 85xx: Remove unused and unconfigured memory test code.Kumar Gala2008-06-11-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused and unconfigured DDR test code from FSL 85xx boards. Besides, other common code exists. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | Socrates: NAND support added. Changed the U-Boot base address andSergei Poselenov2008-06-11-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * | | | | NAND: Added support for 128-bit OOB, adaptedSergei Poselenov2008-06-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * | | | | Socrates: Added FPGA mapping. LAWs and TLBs cleanup.Sergei Poselenov2008-06-11-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * | | | | Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-11-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | Socrates: config file cleanup.Sergei Poselenov2008-06-11-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * | | | | TQM85xx: Change memory map to support Flash memory > 128 MiBWolfgang Grandegger2008-06-11-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| * | | | | TQM85xx: NAND support via local bus UPMBWolfgang Grandegger2008-06-11-3/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. It is now based on the re-written FSL NAND UPM driver. A patch has been posted earlier today with the subject: "NAND FSL UPM: driver re-write using the hwcontrol callback" Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time. Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| * | | | | TQM8548: PCI express supportWolfgang Grandegger2008-06-11-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| * | | | | TQM8548: Basic support for the TQM8548 modulesWolfgang Grandegger2008-06-11-8/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4 Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10. Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
generated by cgit v1.1 at 2024-11-19 16:38:21 +0000