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* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-0/+17
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* MPC85xx: TQM8548: add support for the TQM8548_AG moduleWolfgang Grandegger2009-02-16-2/+9
| | | | | | | | The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory, CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module with "$ make TQM8548_AG_config". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM8548: add support for the TQM8548_BE moduleWolfgang Grandegger2009-02-16-2/+10
| | | | | | | | | The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* MPC85xx: TQM85xx: make standard PCI/PCI-X configurableWolfgang Grandegger2009-02-16-4/+5
| | | | | | | | | The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 86xx: Update CPU info output on bootupPeter Tyser2009-02-16-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Update Global Utilities structurePeter Tyser2009-02-16-8/+21
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Reset updatePeter Tyser2009-02-16-4/+0
| | | | | | | | | | Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-4/+27
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Make some minor whitespace changes to eliminate line-wrappingAndy Fleming2009-02-16-15/+16
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix address map for 36-bit config of MPC8572DSKumar Gala2009-02-16-3/+6
| | | | | | | | | | When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-1/+4
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2009-02-15-14/+0
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| * i2c.h: drop i2c_reg_{read, write} hack for Blackfin partsMike Frysinger2009-02-12-14/+0
| | | | | | | | | | | | | | The Blackfin i2c driver has been rewritten thus the special ifdefs in the common code are no longer needed. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-02-12-10/+4
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| * | ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.hStefan Roese2009-02-12-3/+2
| |/ | | | | | | | | | | | | | | | | | | CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB. It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx boards right now. Signed-off-by: Stefan Roese <sr@denx.de>
* | 82xx, mgcoge: fix compile errorHeiko Schocher2009-02-12-0/+1
|/ | | | | | | | | | | | With actual u-boot compiling the mgcoge port fails, because since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is necessary to define CONFIG_NET_MULTI. Seems to me the mgcoge port is the only actual existing 8260 port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed to be fixed. Signed-off-by: Heiko Schocher <hs@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-02-12-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix whitespace damage: double space changed to a tabJerry Van Baren2009-02-11-3/+3
| | | | | | | | | | At some point an intentional double space at the end of the sentence got changed into a tab in the GPL header line: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the This patch fixes the damage. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-02-11-0/+3
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| * cfi: make flash_get_info() non staticHeiko Schocher2009-02-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | If on your board is more than one flash, you must know the size of every single flash, for example, for updating the DTS before booting Linux. So make this function flash_get_info() extern, and you can have all info about your flashes. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | net: removed board-specific CONFIGs from MPC5xxx FEC driverBen Warren2009-02-09-27/+45
|/ | | | | | | Added new CONFIG options for the three type of MAC-PHY interconnect and applied them all relevant board config files Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala2009-02-10-0/+8
| | | | | | | | Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* Add an architecture specific config.h for common definesKumar Gala2009-02-10-0/+288
| | | | | | | | | | We have common defines that we duplicate in various ways. Having an arch specific config.h gives us a common location for those defines. Eventually we should be able to replace this when we have proper Kconfig support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8641hpcn: Change PCI MEM pci bus addressBecky Bruce2009-02-10-1/+10
| | | | | | | | | | Now that the rest of u-boot can support it, change the PCI bus address of the PCI MEM regions from 0x80000000 to 0xc0000000, and use the same bus address for both PCI1 and PCI2. This will maximize the amount of PCI address space left over to map RAM on systems with large amounts of memory. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* MPC8641HPCN: Enable CONFIG_ADDR_MAPBecky Bruce2009-02-10-0/+2
| | | | Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc8641hpcn: Clean up PCI mapping conceptsBecky Bruce2009-02-10-6/+11
| | | | | | | | | Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc86xx: Add support to populate addr map based on BATsBecky Bruce2009-02-10-3/+13
| | | | | | | If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* powerpc: Move duplicated BAT defines to mmu.hBecky Bruce2009-02-10-165/+44
| | | | | | | | | | | The BAT fields are architected; there's no need for these to be in cpu-specific files. Drop the duplication and move these to include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only used by the alaska board, and switch to using the BATU_BL_xxx defines used by all the other boards. The BL_ defines previously in use had to be shifted into the proper position for use, which was inefficient. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* drivers/pci: Create pci_map_bar functionBecky Bruce2009-02-10-4/+24
| | | | | | | | It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc8641hpcn: Use physical address in flash banks defintionBecky Bruce2009-02-10-1/+1
| | | | | | | If the VA and PA of the flash aren't the same, the banks list should be initialized to hold the physical address. Correct this. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-1/+1
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2009-02-07-12/+113
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| * Coldfire: M527x: Add missing GPIO register address definesRichard Retanubun2009-02-06-0/+32
| | | | | | | | | | | | Add missing GPIO registers address definition for Coldfire M5271. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: M5271EVB: Board header update (dependencies)Richard Retanubun2009-02-06-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup for M5271EVB: Added clarification on the use of CONFIG_SYS_CLOCK. Modified to use u-boot's HUSH parser. Cleanup on environment settings. Removed compiler warning by defining CONFIG_SYS_CS0_* Dependencies: Added the use of CONFIG_SYS_MCF_SYNCR for clock multiplier. This depends on a patch to include/asm-m68k/m5271.h that defines the multiplier and divider ratios. Removed the definition of CONFIG_SYS_FECI2C. This depends on a patch that removes the use of it in cpu/mcf52x2/cpu_init.c Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: M5271: Allow board header file to specify clock multiplierRichard Retanubun2009-02-06-2/+51
| | | | | | | | | | | | | | | | | | M5271 dynamic clock multiplier. It is currently fixed at 100MHz. Allow the board header file to set their own multiplier and divider. Added the #define for the multiplier and divider to the cpu header file. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-02-07-84/+222
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| * | Blackfin: move default boot SPI CS to common codeMike Frysinger2009-02-05-0/+9
| | | | | | | | | | | | | | | | | | | | | Move the default SPI CS that we boot from into common code so that it can be used in other SPI drivers and environment settings. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: update anomaly listsMike Frysinger2009-02-03-84/+213
| |/ | | | | | | | | | | Update the anomaly lists to match latest anomaly sheets. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-02-07-1/+1
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| * | flash/cfi_flash: Use virtual sector start address, not physBecky Bruce2009-02-05-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | include/flash.h was commented to say that the address in flash_info->start was a physical address. However, from u-boot's point of view, and looking at most flash code, it makes more sense for this to be a virtual address. So I corrected the comment to indicate that this was a virtual address. The only flash driver that was actually treating the address as physical was the mtd/cfi_flash driver. However, this code was using it inconsistently as it actually directly dereferenced the "start" element, while it used map_physmem to get a virtual address in other places. I changed this driver so that the code which initializes the info->start field calls map_physmem to get a virtual address, eliminating the need for further map_physmem calls. The code is now consistent. The *only* place a physical address should be used is when defining the flash banks list that is used to initialize the flash_info struct, usually found in the board config file. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2009-02-07-2/+131
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| * ADS5121 Add PATA supportRalph Kondziella2009-02-03-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | Original patch from Ralph Kondziella plus clean up by Wolfgang Denk plus changes by John Rigby use ips clock not lpc port forward to current u-boot release Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: John Rigby <jrigby@freescale.com>
| * ADS5121 Add IC Ident Module (IIM) supportMartha Marx2009-02-03-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | IIM (IC Identification Module) is the fusebox for the mpc5121. Use #define CONFIG_IIM to turn on the clock for this module use #define CONFIG_CMD_FUSE to add fusebox commands. Fusebox commands include the ability to read the status, read the register cache, override the register cache, program the fuses and sense them. Signed-off-by: Martha Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
| * ADS5121 DIU Make inclusion of FSL logo optionalJohn Rigby2009-02-03-0/+1
| | | | | | | | | | | | | | Make inclusion of FSL logo optional and turn it off by default. Signed-off-by: John Rigby <jrigby@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2009-02-03-0/+2
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| * | Compile warning fix in onenand_uboot.hRemy Bohmer2009-02-02-0/+2
| |/ | | | | | | | | | | Regression since merge window after 2009.01 Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | Blackfin: add driver for on-chip MMC/SD controllerCliff Cai2009-02-02-0/+123
| | | | | | | | | | | | | | This is a port of the Linux Blackfin on-chip SDH driver to U-Boot. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: output booting source when bootingMike Frysinger2009-02-02-0/+22
| | | | | | | | | | | | | | Knowing the booting source of the part is useful, especially when the part can switch dynamically between sources. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: set default CONFIG_ENV_SPI_CS based on bootromMike Frysinger2009-02-02-0/+5
| | | | | | | | | | | | | | Set the default CONFIG_ENV_SPI_CS value to match the SPI CS that is used by the Blackfin on-chip bootrom to boot out of SPI flash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
generated by cgit v1.1 at 2024-12-22 07:16:20 +0000