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* ppc4xx: Consolidate pci_master_init() functionStefan Roese2009-11-19-0/+1
| | | | | | | | This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-1/+10
| | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_target_init() functionStefan Roese2009-11-19-2/+8
| | | | | | | | | | This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* Merge branch 'master' into nextWolfgang Denk2009-11-15-8/+147
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| * Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-11-11-3/+1
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| | * Fix SMC91111 regression: lpd7a40x build failuresBen Warren2009-11-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both lpd7a400 and lpd7a404 failed to compile because they had CONFIG_SMC_USE_IOFUNCS defined: examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw' Also removed an orphaned paren in lpd7a404.h Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-11-11-1/+1
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| | * | ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem only seen very occasionally on Canyonlands. The NOR flash interface (CFI driver) doesn't work reliably in all cases. Erasing and/or programming sometimes doesn't work. Sometimes with an error message, like "flash not erased" when trying to program an area that should have just been erased. And sometimes without any error messages. As mentioned above, this problem was only seen rarely and with some PLL configuration (CPU speed, EBC speed). Now I spotted this problem a few times, when running my Canyonlands with the following setup (chip_config): 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 Changing the EBC configuration to not release the bus into high impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1 in EBC0_CFG) seems to fix this problem. I haven't seen any failure anymore with this patch applied. Signed-off-by: Stefan Roese <sr@denx.de> Cc: David Mitchell <dmitchell@amcc.com> Cc: Jeff Mann <MannJ@embeddedplanet.com>
| * | | Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-11-09-1/+142
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| | * | | ARM: Use Linux version for unaligned access codeRemy Bohmer2009-11-07-1/+142
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The asm-arm/unaligned.h includes linux/unaligned/access_ok.h This file is unsafe to be used on ARM, since it does an unaligned memory accesses which fails on ARM. Lookin at Linux the basic difference seems to be the header "include/asm-arm/unaligned.h". The Linux version of "unaligned.h" does *not* include "access_ok.h" at all. It includes "le_byteshift.h" and "be_byteshift.h" instead. Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Stefan Roese <sr@denx.de> -- include/asm-arm/unaligned.h | 3 - include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++ include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++ 3 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 include/linux/unaligned/be_byteshift.h create mode 100644 include/linux/unaligned/le_byteshift.h
| * | | fsl_pci_init_port end-point initialization is brokenEd Swarthout2009-11-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-2/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | sbc8349: fix incorrect commentWolfgang Denk2009-10-28-1/+1
| |/ | | | | | | | | | | | | | | The comment for the BR0_PRELIM port size initialization incorrectly stated 32 bit, while it's actually 16 bit. The code is correct. Reported-by: Guenter Koellner <guenter.koellner@nsn.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ENV Variable support for Flex-OneNANDAmul Kumar Saha2009-11-13-0/+2
| | | | | | | | | | | | | | | | Define and use CONFIG_ENV_ADDR_FLEX and CONFIG_ENV_SIZE_FLEX for storing environment variables. Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com> Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
* | Flex-OneNAND driver supportAmul Kumar Saha2009-11-13-3/+41
| | | | | | | | | | | | | | This patch adds support for Flex-OneNAND devices. Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com> Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
* | NAND: Update to support 64 bit device sizeSandeep Paulraj2009-11-13-3/+3
| | | | | | | | | | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | ppc4xx: Katmai: Add chip_config commandStefan Roese2009-11-10-1/+8
| | | | | | | | | | | | | | This patch removes the Katmai "bootstrap" command and replaces it with the now common command "chip_config". Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add UBI support to PLU405 boardsMatthias Fuchs2009-11-10-4/+14
| | | | | | | | | | | | | | | | | | -add UBI support -increase malloc'able memory size -cleanup MONITOR|FLASH_BASE|LEN constants Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-0/+8
| | | | | | | | | | | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: sc3: Remove unreferenced external declarations from sc3.hStefan Roese2009-11-02-5/+0
| | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | mpc52xx: add support for the IPEK01 boardWolfgang Grandegger2009-10-31-0/+408
| | | | | | | | | | | | | | This patch adds support for the board IPEK01 based on the MPC5200. The Futjitsu Lime graphics controller is configured in 16 bpp mode. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* | Merge branch 'next' of git://git.denx.de/u-boot-video into nextWolfgang Denk2009-10-31-6/+18
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| * | video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01Wolfgang Grandegger2009-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words for D32 accesses due to the diffferent connecting to the GDC bus. This patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP, which should be set for all board using the mb862xx in 16 bpp mode. For the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * | video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp modeAnatolij Gustschin2009-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new IPEK01 board can use the 32 bpp mode for the Lime graphics controller. For this mode, video accelaration does not work. This patch makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL, which is enabled for the lwmon5 and the socrates board for backward compatibility. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
| * | video: mb862xx: improve board-specific Lime configurationWolfgang Grandegger2009-10-31-6/+14
| |/ | | | | | | | | | | | | | | | | | | | | To avoid board-specific code accessing the mb862xx registers directly, the public function mb862xx_probe() has been introduced. Furthermore, the "Change of Clock Frequency" and "Set Memory I/F Mode" registers are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR, respectively. The BSPs for the socrates and lwmon5 boards have been adapted accordingly. Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* | new PCA9564 i2c bridge driverValentin Yakovenkov2009-10-30-0/+50
|/ | | | | Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-10-28-0/+157
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| * cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
* | Fix Compliation warning for TNY-A9260 and TNY-A9G20Sandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Fix Compliation warning for SBC35-A9G20 boardSandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | galaxy5200: Add default environment variablesEric Millbrandt2009-10-28-2/+8
|/ | | | | | | Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add 'editenv' commandPeter Tyser2009-10-27-0/+2
| | | | | | | | | The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-10-27-1/+59
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| * mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+23
| | | | | | | | | | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * xpedite5370: Enable multi-core supportPeter Tyser2009-10-27-0/+8
| | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Revert "env: only build env_embedded and envcrc when needed"Wolfgang Denk2009-10-27-5/+0
|/ | | | | | Breaks building on many boards, and no really clean fix available yet. This reverts commit 6dab6add2d8ee80905234b326abc3de11be1d178.
* Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-10-24-1215/+1763
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| * s5pc1xx: SMDKC100: fix compile warningsMinkyu Kang2009-10-24-112/+112
| | | | | | | | | | | | | | fix the following compile warnings warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * TI OMAP3 SDP3430: Initial SupportTom Rix2009-10-24-0/+369
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start of support of Texas Instruments Software Development Platform(SDP) for OMAP3430 - SDP3430 Highlights of this platform are: Flash Memory devices: Sibley NOR, Micron 8bit NAND and OneNAND Connectivity: 3 UARTs and expanded 4 UART ports + IrDA Ethernet, USB Other peripherals: TWL5030 PMIC+Audio+Keypad VGA display Expansion ports: Memory devices plugin boards (PISMO) Connectivity board for GPS,WLAN etc. Completely configurable boot sequence and device mapping etc. Support default jumpering and: - UART1/ttyS0 console(legacy sdp3430 u-boot) - UART3/ttyS2 console (matching other boards, and SDP HW docs) - Ethernet - mmc0 - NOR boot Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9. Conflicts: Makefile Fixed the conflict with smdkc100_config by moving omap_sdp3430_config to it is alphabetically sorted location above zoom1. Signed-off-by: David Brownell <david-b@pacbell.net> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * TI DaVinci: Adding Copyright for DM365 EVMSandeep Paulraj2009-10-24-0/+1
| | | | | | | | | | | | | | Forgot to add Copyright while submitting the patch. This patch adds the copyright. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci: Fix DM6467 EVM Compilation WarningSandeep Paulraj2009-10-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI OMAP3: make gpmc_config as constNishanth Menon2009-10-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP3: export enable_gpmc_cs_config to board filesNishanth Menon2009-10-18-0/+2
| | | | | | | | | | | | | | | | | | Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config' Signed-off-by: Nishanth Menon <nm@ti.com>
| * TI DaVinci Sonata: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DVEVM: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * TI DaVinci DM365: Add Config option for 64 bit SupportSandeep Paulraj2009-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config. Without this option enabled while performing NAND operations we will get wrong diagnostic messages. Example if the MTD NAND driver find a bad block while erasing from a certain address, it will say bad block skipped at 0x00000000. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
generated by cgit v1.1 at 2024-11-10 23:29:44 +0000