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* usb: mpc834x: added support of the MPH USB controller in addition to the DR oneValeriy Glushkov2009-07-14-1/+10
| | | | | Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: set 64BIT_VSPRINTF for boards using nand_utilKim Phillips2009-07-14-0/+4
| | | | | | | | | | | When enabling NAND support for a board, one must also define CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c for correct output. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Ron Madrid <ron_madrid@sbcglobal.net> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc5121ads: add JFFS2 and MTDPARTS support; adjust flash mapWolfgang Denk2009-07-14-8/+38
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* aria: add JFFS2 and MTDPARTS support; adjust flash mapWolfgang Denk2009-07-14-5/+34
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* aria: enable NAND flash supportWolfgang Denk2009-07-14-1/+23
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MPC512x: fix typo in comment listing the NAND driver nameWolfgang Denk2009-07-14-2/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* mecp5123: cleanup - remove dead codeWolfgang Denk2009-07-14-7/+0
| | | | | | | | Remove dead code that was obviously a left-over from copy & paste. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* aria: adjust memory controller initializationWolfgang Denk2009-07-14-13/+72
| | | | | | Needed for Rev. 2 silicon at 400 MHz Signed-off-by: Wolfgang Denk <wd@denx.de>
* MPC512x: factor out common codeWolfgang Denk2009-07-14-0/+57
| | | | | | | | | | | | | | Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* MPC512x: Add MSCAN1...4 Clock Control RegistersWolfgang Denk2009-07-14-4/+5
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* MPC512x: enabling NAND support requires CONFIG_SYS_64BIT_VSPRINTFWolfgang Denk2009-07-14-0/+4
| | | | | | | | | | When enabling NAND support for a board, one must also define CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c for correct output. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2009-07-14-108/+813
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| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-26/+613
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| | * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-26/+613
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| | | * versatile: update config and merge to cfi flash driverJean-Christophe PLAGNIOL-VILLARD2009-07-12-15/+50
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Peter Pearse <peter.pearse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com>
| | | * versatile: specify the board type on the promptJean-Christophe PLAGNIOL-VILLARD2009-07-12-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Peter Pearse <peter.pearse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com>
| | | * at91: Introduction of at91sam9g10 SOC.Sedji Gaouaou2009-07-12-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | | * at91: Introduction of at91sam9g45 SOC.Sedji Gaouaou2009-07-12-0/+532
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | | * pxa: fix CKEN_B register bitsDaniel Mack2009-07-12-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current defition for CKEN_B register bits is nonsense. Adding 32 to the shifted value is equal to '| (1 << 5)', and this bit is marked 'reserved' in the PXA docs. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| | | * pxa: add clock for system bus 2 arbiterDaniel Mack2009-07-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is needed for systems using the USB2 device unit or the 2d graphics accelerator. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| | | * arm: Kirkwood: bugfix: UART1 bar correctionPrafulla Wadaskar2009-07-12-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-21/+185
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| | * | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-07-13-21/+185
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| | | * | sh: Update pci config for Renesas r7780mp boardNobuhiro Iwamatsu2009-07-11-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | sh: Add support ESPT-GIGA boradNobuhiro Iwamatsu2009-07-11-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ESPT-Giga is SH7763-based reference board. Board support is relatively sparse, presently supporting serial, gigabit ethernet, USB host, and MTD. More information (in Japanese) available at: http://www.cente.jp/product/cente_hard/ESPT-Giga.html Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | sh: Revised the build with newest compilerNobuhiro Iwamatsu2009-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check of data became severe from newest gcc. This patch checked in gcc-4.2 and 4.3 . Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | sh3/sh4: rename config option TMU_CLK_DIVIDER to CONFIG_SYS_TMU_CLK_DIVJean-Christophe PLAGNIOL-VILLARD2009-07-08-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | sh3/sh4: fix CONFIG_SYS_HZ to 1000Jean-Christophe PLAGNIOL-VILLARD2009-07-08-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | sh: introduce clock frameworkJean-Christophe PLAGNIOL-VILLARD2009-07-08-0/+35
| | | |/ | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-2/+2
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| | * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-07-13-2/+2
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| | | * | ppc4xx: Make is_pci_host() available for all 440 and 405 CPUsMatthias Fuchs2009-07-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-5/+9
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| | * | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-07-13-5/+9
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| | | * | | Blackfin: cm-bf561: add example settings for EXT-BF5xx-USB-ETH2 add-onHarald Krapfenbauer2009-07-10-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cm-bf561 module can easily hook up to the EXT-BF5xx-USB-ETH2 extender board, so add a simple example of how to do that in the board config. Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | | * | | Blackfin: blackstamp: update spi flash settingsMike Frysinger2009-07-10-5/+4
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest blackstamp boards can only run the SPI flash at 15MHz before they start to crap out, so lower the max speeds accordingly. The new SPI flash also has different sector requirements, so update the environment sizes as well. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-1/+1
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| | * | | usb: fix CONFIG_SYS_MPC83xx_USB_ADDR not defined errorKim Phillips2009-07-09-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix a stray CONFIG_MPC83XX that escaped commit 0f898604945af4543c1525fc33b6bae621a3b805. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | Add ESD PCI vendor IDMatthias Fuchs2009-07-11-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| * | | remove _IO_BASE and KSEG1ADDR from board configuration filesTimur Tabi2009-07-11-53/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet driver, but the code that used that macro was removed over a year ago, so board configuration files no longer need to define it. The _IO_BASE macro is also automatically defined to 0 if it isn't already set, so there's no need to define that macro either in the board configuration files. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | | board support patch for phyCORE-MPC5200B-tinyJon Smirl2009-07-10-0/+444
|/ / | | | | | | | | | | | | | | | | | | Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-08-0/+2
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| * \ Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-07-08-0/+2
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| | * | ppc4xx: Fix FDT EBC mappings on CanyonlandsFelix Radensky2009-07-08-0/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-08-156/+38
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| * | nand_spl: read environment early, when booting from NAND using nand_splGuennadi Liakhovetski2009-07-07-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when booting from NAND using nand_spl, in the beginning the default environment is used until later in boot process the dynamic environment is read out. This way environment variables that must be interpreted early, like the baudrate or "silent", cannot be modified dynamically and remain at their default values. Fix this problem by reading out main and redundand (if used) copies of the environment in the nand_spl code. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: nand: use loff_t for offsetJean-Christophe PLAGNIOL-VILLARD2009-07-07-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | nand_util currently uses size_t which is arch dependent and not always a unsigned long. Now use loff_t, as does the linux mtd layer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: nand: new base driver for memory mapped nand devicesMike Frysinger2009-07-07-26/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | The BF537-STAMP Blackfin board had a driver for working with NAND devices that are simply memory mapped. Since there is nothing Blackfin specific about this, generalize the driver a bit so that everyone can leverage it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | davinci_nand chipselect/init cleanupDavid Brownell2009-07-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | NAND DaVinci: Update to ALE/CLE Mask valuesSandeep Paulraj2009-07-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
generated by cgit v1.1 at 2024-11-16 04:04:07 +0000