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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-18/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: Remove all CONFIG_SYS_* fpga related optionsMichal Simek2013-05-06-24/+0
| | | | | | | | All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: Check device name against bitstream nameMichal Simek2013-05-06-0/+1
| | | | | | | | Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-0/+4
| | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* fpga: constify to fix build warningWolfgang Denk2011-08-01-3/+3
| | | | | | | | | | | | | | | Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
* add block write function to spartan3 slave serial loadWolfgang Wegner2010-03-24-0/+1
| | | | | | | | | | | Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* fpga: Remove relocation fixupsPeter Tyser2009-10-03-1/+0
| | | | | | | | PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-14/+14
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-34/+34
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Improve configuration of FPGA subsystemMatthias Fuchs2008-01-09-2/+2
| | | | | | | | | | | | | This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Add Xilinx Spartan3 family FPGA supportWolfgang Denk2005-09-25-0/+3
| | | | Patch by Kurt Stremerch, 14 February 2005
* Initial revisionwdenk2002-11-03-0/+102
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