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* NET: Base support for etsec2.0Kumar Gala2010-01-05-0/+7
| | | | | | | | | | 1. Modified the tsec_mdio structure to include the new regs 2. Modified the MDIO_BASE_ADDR so that it will handle both older version and new version of etsec. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NET: Move MDIO regs out of TSEC SpaceSandeep Gopalpet2010-01-05-22/+23
| | | | | | | | | | | | | | | | | Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into platform specific files. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* tsec: Add support for BCM5482S PHYZach LeRoy2009-06-15-0/+2
| | | | | | Signed-off-by: Zach LeRoy <zleroy@xes-inc.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xxPeter Tyser2009-06-12-1/+1
| | | | | | | | Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* net: tsec: Fix Marvell 88E1121R phy initAnatolij Gustschin2008-12-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init: Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-5/+5
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Coding style cleanup, update CHANGELOGWolfgang Denk2008-09-13-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add SGMII support to the tsecAndy Fleming2008-09-02-1/+24
| | | | | | | Adds support for configuring the TBI to talk properly with the SerDes. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-4/+28
| | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* tsec: Move tsec.h to include/Andy Fleming2008-09-02-0/+592
This is to prepare the way for board code passing in the tsec_info structure Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>