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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-18/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: add definition for Xilinx Spartan-6 XC6SLX4Stefano Babic2012-01-05-0/+9
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* fpga: constify to fix build warningWolfgang Denk2011-08-01-3/+3
| | | | | | | | | | | | | | | Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
* add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fnsWolfgang Wegner2010-11-30-0/+1
| | | | | | | | Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
* add block write function to spartan3 slave serial loadWolfgang Wegner2010-03-24-0/+1
| | | | | | | | | | | Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* fpga: Remove relocation fixupsPeter Tyser2009-10-03-3/+0
| | | | | | | | PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Fix Spartan-3 definitions.Laurent Pinchart2008-09-22-3/+3
| | | | | | | A few Spartan-3 definitions erroneously use Spartan-3E size constants. This patch fixes them. Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
* Remove duplicate Spartan-3E definition.Laurent Pinchart2008-09-22-9/+0
| | | | | Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-11/+11
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add new Xilinx Spartan FPGA typesMatthias Fuchs2008-01-09-1/+9
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Add pre and post configuration callbacks for Spartan FPGAsMatthias Fuchs2008-01-09-0/+1
| | | | | | | | This patch adds a post configuration callback for Spartan2/3 FPGAs. pre and post configuration callback are now optional and not called when the function pointer is set to NULL. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* add image size and descriptors for Spartan 3E FPGA chipsBruce Adler2007-08-11-0/+24
| | | | | | Spartan 3E image sizes taken from Table 1-4 in Xilinx UG332 (v1.1) Signed-off by: Bruce Adler <bruce.adler@ccpu.com>
* Add Xilinx Spartan3 family FPGA supportWolfgang Denk2005-09-25-0/+103
Patch by Kurt Stremerch, 14 February 2005
generated by cgit v1.1 at 2024-11-01 10:32:11 +0000