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* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-47/+0
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Continue cleanup of ppc440.hStefan Roese2008-07-11-302/+3
| | | | | | | This patch continues the ppc440.h cleanup by removing some of the unused defines. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-708/+0
| | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate PPC4xx EBC definesStefan Roese2008-07-11-87/+0
| | | | | | | | | | | This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial 460SX reference board (redwood) config file and defines.Feng Kan2008-07-11-7/+13
| | | | | Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 460EX errata with CPU lockup upon high AHB trafficStefan Roese2008-06-30-0/+2
| | | | | | | | | | | | | | | This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1Stefan Roese2008-06-03-896/+0
| | | | | | | | | | | | | | | | | | | This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* lwmon5: watchdog POST fixYuri Tikhonov2008-04-25-0/+7
| | | | | | | | | Use the GPT0_MASKx registers as the temporary storage for watch-dog timer POST test instead of GPT0_COMPx. The latter (GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* ppc4xx: Fix power mgt definitions for PPC440Eugene O'Brien2008-04-11-8/+1
| | | | | | Corrected DCR addresses of PPC440EP power management registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
* ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-0/+4
| | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
* The patch introduces the alternative configuration of the log buffer for the ↵Yuri Tikhonov2008-03-18-0/+2
| | | | | | | | | | | | | | lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). To enable this, alternative, configuration the U-Boot board configuration file for lwmon5 includes the definitions of alternative addresses for header (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* The patch adds new POST tests for the Lwmon5 board. These are:Yuri Tikhonov2008-03-18-0/+3
| | | | | | | | | | | * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval boardStefan Roese2008-03-15-0/+3
| | | | | | | This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (5/5)Stefan Roese2008-03-15-88/+502
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'lwmon5-no-ocm'Stefan Roese2008-01-09-3/+1
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| * ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymoreStefan Roese2008-01-09-3/+1
| | | | | | | | | | | | | | This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-2/+10
|/ | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* Add definitions for 440EPx/GRx SDRAM controller to ppc440.hLarry Johnson2007-12-27-48/+466
| | | | | | | | | This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boardsStefan Roese2007-12-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com> from AMCC and slighly changed. Signed-off-by: Pravin M. Bathija <pbathija@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-28/+0
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-4/+2
| | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-87/+0
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update 440EPx lwmon5 board supportStefan Roese2007-07-31-0/+13
| | | | | | | | - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-2/+0
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-2/+4
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-4/+4
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* Extend POST support for PPC440Igor Lisitsin2007-06-22-24/+26
| | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* Merge with /home/stefan/git/u-boot/denx-440-exceptionsStefan Roese2007-06-15-4/+1
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| * ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Add initial lwmon5 board supportStefan Roese2007-06-15-1/+4
|/ | | | | | | This patch adds initial support for the Liebherr lwmon5 board euqipped with an AMCC 440EPx PowerPC. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add mtcpr/mfcpr access macrosStefan Roese2007-05-11-3/+17
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add output for bootrom location to 405EZ portsStefan Roese2007-04-18-1/+1
| | | | | | | | | | | | | | Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-23/+0
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| * [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-23/+0
| | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-1/+24
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| * | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-1/+24
| |/ | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-8/+8
|/ | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-2/+4
| | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-2/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)Stefan Roese2007-01-05-9/+11
| | | | | | | This fix will make the MAL burst disabling patch for the Linux EMAC driver obsolete. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] include/ppc440.h minor error affecting interruptsStefan Roese2006-11-29-18/+18
| | | | | | | | | | Fixed include/ppc440.c for UIC address Bug Corrects bug affecting the addresses for the universal interrupt controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips. Signed-off-by: Jeff Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/denxStefan Roese2006-11-10-2/+2
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| * Fix comments in include/ppc440.hWolfgang Denk2006-09-20-2/+2
| | | | | | | | Patch by Martin Hicks, 16 Jun 2006
* | Merge with /home/stefan/git/u-boot/denxStefan Roese2006-09-18-28/+581
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| * Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-28/+581
| | | | | | | | | | | | | | | | | | | | | | - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
* | Add initial support for the ALPR board from ProdriveStefan Roese2006-08-15-1/+1
|/ | | | | NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
* Fix CONFIG_440_GX define usage.Marian Balakowicz2006-06-30-6/+3
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* Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-12/+1289
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